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| 型號(hào)： | IBM21P100BGC |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 61/144頁(yè) |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_operations.fm.01
October 15, 2001
Bus Operation
Page 23 of 144
3.2 Write Transactions
Write transactions are treated as either posted, delayed/split (PCI-X), or immediate write transactions as
shown in
3.2.1 Posted Write Transactions
The posted mode is the default mode used for the memory-write and memory-write-and-invalidate transac-
tions. The memory-write-block transaction also uses the posted mode. Posted is the only mode used for the
memory-write-block command.
When the IBM 133 PCI-X Bridge R2.0 determines that a memory write transaction is to be forwarded across
the bridge, it first checks for empty space in the posted write buffer. If space is available in the posted write
buffer, the bridge accepts data until the buffer is full or the transaction is terminated. If the transaction is termi-
nated because the buffer is full, the transaction is terminated on a 128-byte boundary. If there is no space in
the posted write buffer, the transaction is terminated with retry.
Up to eight posted write transactions can be enqueued on the bridge.
3.2.1.1 PCI to PCI-X Transactions
When the originating bus is operating in the conventional PCI mode and the destination bus is operating in
the PCI-X mode, the bridge must buffer memory write transactions from the conventional PCI interface and
count the number of bytes to be forwarded to the PCI-X interface. If the conventional PCI transaction uses the
memory write command and some byte enables are not asserted, the bridge must use the PCI-X memory
write command. If the conventional PCI command is memory write and all byte enables are asserted, the
bridge will use the memory write PCI-X command. If the conventional transaction uses the memory write and
invalidate command, the bridge uses the PCI-X memory write block command.
The bridge attempts to transfer the write data on the PCI-X interface as soon as the transaction ends or a
128-byte boundary is crossed, whichever comes first. Writes of greater than 128 bytes are possible only if
more than one 128-byte sector fills up before the write operation is issued on the PCI-X interface.
3.2.1.2 PCI-X to PCI Transactions
When the originating bus is operating in the PCI-X mode and the destination bus is operating in the conven-
tional PCI mode, the bridge uses the conventional memory write command for both the PCI-X memory write
and PCI-X memory write block commands.
Table 3-3. Write Transaction Handling
Type of Transaction
Type of Handling
Memory Write
Posted
Memory Write and Invalidate
Posted
Memory Write Block (PCI-X)
Posted
I/O Write
Delayed/Split (PCI-X)
Type 0 Configuration Write
Immediate on the primary bus, Delayed/Split (PCI-X) on the sec-
ondary bus.
Type 1 Configuration Write
Delayed/Split (PCI-X)
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