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參數(shù)資料
| 型號： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 72/144頁 |
| 文件大小： | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_ordering.fm.01
October 15, 2001
Transaction Ordering
Page 33 of 144
4. Transaction Ordering
To maintain data coherence and consistency, the IBM 133 PCI-X Bridge R2.0 complies with the ordering
rules set forth in the
PCI Local Bus Specification, Revision 2.2 for the PCI mode and the PCI-X Addendum to
the PCI Local Bus Specification, Revision 1.0 for the PCI-X mode.
This chapter describes the ordering rules that control transaction forwarding across the bridge. For a more
detailed discussion of transaction ordering see Appendix E of the
PCI Local Bus Specification, Revision 2.2
for the PCI mode and Section 8.4.4 of the
PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0
for the PCI-X mode.
4.1 General Ordering Guidelines
Independent transactions on the primary and secondary buses have a relationship only when those transac-
tions cross the IBM 133 PCI-X Bridge R2.0.
The following general ordering guidelines govern transactions crossing the bridge:
Requests terminated with target retry can be accepted and completed in any order with respect to other
transactions that have been terminated with target retry. If the order of delayed or split requests is impor-
tant, the initiator should not start a second delayed or split transaction until the first transaction has been
completed. If more than one delayed or split transaction is initiated, the initiator should repeat all retried
requests, using some fairness algorithm. Repeating a delayed or split transaction cannot be contingent
upon the completion of another delayed transaction; otherwise, a deadlock can occur.
Write transactions flowing in one direction have no ordering requirements with respect to write transac-
tions flowing in the opposite direction. The bridge can accept posted write transactions on both interfaces
at the same time, and also can initiate posted write transactions on both interfaces at the same time.
The acceptance of posted memory or memory write transactions as a target can never be contingent on
the completion of a non-locked, non-posted transaction as a master. This is true of the bridge and must
also be true of other bus agents; otherwise, a deadlock can occur.
The bridge accepts posted memory or memory write transactions, regardless of the state of completion of
any delayed or split transactions being forwarded across the bridge.
4.2 Ordering Rules
Table 4-1 and Table 4-2 describe the ordering rules for the IBM 133 PCI-X Bridge R2.0 in the PCI-X and the
PCI modes.
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