參數(shù)資料
型號(hào): IBM21P100BGC
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA304
封裝: 31 X 31 MM, PLASTIC, BGA-304
文件頁數(shù): 138/144頁
文件大小: 5197K
代理商: IBM21P100BGC
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_pcix_regs.fm.01
October 15, 2001
Configuration Registers
Page 93 of 144
5.2.5.27 PCI-to-PCI Bridge Support Extensions Register
This register is read only and indicates that the bridge will not stop the clocks on a change of power state.
5.2.5.28 Data Register
This register is read only, since the bridge does not implement the data register.
Address Offset
x‘96’
Access
Read only
Reset Value
x‘00’
B
u
s
P
o
w
er
/C
lo
ck
C
o
nt
ro
l
E
na
b
le
B
2
/B
3
S
up
por
t
for
D
3
ho
t
Reserved
7
6
5
4
3
2
1
0
Bit(s)
Access
FieldNameand Description
7
RO
Bus Power/Clock Control Enable
Forced to b‘0’ to indicate that the secondary clock cannot be controlled by this device and that the power/clock
control capabilities have been disabled.
6
RO
B2 B3# (B2/B3 support for D3hot)
Forced to b‘0’ and has no meaning because bit 7 indicates that the power/clock control capabilities have been
disabled.
5:0
RO
Reserved.
Address Offset
x‘97’
Access
Read Only
Reset Value
x‘00’
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