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| 型號： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 8/144頁 |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_clock_reset.fm.01
October 15, 2001
Clocking and Reset
Page 105 of 144
In
Table 6-2,the terms “P_cycles” and “S_cycles” refer to clock cycles whose period is determined by the
P_CLK and S_CLK input frequencies, respectively. Since the time periods listed in the table are based on
counters, different clock rates will result in different effective delays, as shown. The counter values have been
selected to meet the various minimum delay requirements, but will result in longer times when the clock
period lengthens.
6.7 Bus Parking and Bus Width Determination
On the secondary interface, as required by the
PCI-to-PCI Bridge Specification, the S_AD(31:0),
S_C/BE(3:0), and PAR signals will be driven to zeros whenever S_RST# is asserted. This is known as bus
parking. The signals are driven low within a few cycles of the falling edge of S_RST#; they are released
(placed in the high-Z state) in the cycle following the rising edge of S_RST#.
The bridge is also required to drive S_REQ64# low for at least ten cycles prior to the de-assertion of S_RST#,
to allow devices to determine whether they are connected on a 64-bit data path or a 32-bit data path. For
convenience, this is done coincident with the broadcasting of the initialization pattern, as shown in
and
6.8 Power Management and Hot-Plug
The IBM 133 PCI-X Bridge R2.0 is compliant with the minimum requirements of the
PCI Power Management
Interface Specification, as it supports the D0 and D3 power management states and the power management
capabilities registers. No other power management functions are implemented by the bridge. Power manage-
ment events (PMEs) are not supported.
The transition into a D3 power management state by the bridge will be the result of either a software action or
the removal of power. The D3 state has two variants that are supported, D3hot and D3cold. When the bridge
transitions from the D0 state to the D3hot state, the secondary bus signals are driven to their benign state and
the bridge only accepts Type 0 configuration transactions on the primary interface. On the transition from the
D3hot to the D0 state, all configuration registers are returned to their reset values without the generation of a
secondary side PCI reset (S_RST#). The generation of a secondary side PCI reset after transitioning to the
DO state is supported by software writing to the bridge control register x'3E' bit 6.
Thetransitiontothe D3cold state occurs when power is removed from the device. The bridge will be in the
uninitialized D0 state once power is reapplied and the power-on sequences associated with P_RST# and
S_RST# described in
Section 6.6.1 and Section 6.6.2 are complete. These power-on sequences require soft-
ware to fully initialize and configure the bridge.
The bridge contains no functions to specifically assist or preclude its use in a hot-plug system. In such an
environment, each hot-plug slot must be independently controlled via an external hot-plug controller. Such a
controller is required to perform the various initialization and reset functions described above for the slots
under its control. In addition, before connecting those slots to the rest of the bus, it must assure that the capa-
bilities of devices plugged into the slots match the mode and operating frequency of the bus. Presumably, the
hot-plug controller will need to remember the initialization pattern broadcast at the last bus reset. If it detects
a device with the same or greater capability than what the bus is running, it should initialize the card with the
stored pattern before connecting to the bus. If it detects a lower capability, then a bus reset is required and
the entire bus must be reconfigured.
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