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參數(shù)資料
| 型號： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 62/144頁 |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Bus Operation
Page 24 of 144
ppb20_operations.fm.01
October 15, 2001
The bridge attempts to transfer write data on the conventional PCI interface when the PCI-X data crosses a
128-byte boundary or the end of the PCI-X transfer occurs, whichever comes first. As long as a 128-byte
buffer is full, or the end of transfer remains from the PCI-X memory write command when a 128-byte
boundary is crossed, the transfer will continue on the conventional PCI interface.
3.2.1.3 PCI to PCI Transactions
When both buses are operating in conventional PCI mode, the bridge passes the memory write command
that it receives to the destination interface, unless the bridge is disconnected in the middle of a memory write
and invalidate and is not on a cache line boundary. In this event, the command will continue as a memory
write when the bridge attempts to reconnect.
The bridge attempts to transfer a memory write command when the transaction ends or a 128-byte boundary
is crossed, whichever comes first. As long as a 128-byte buffer is full or the end of transfer remains from the
PCI memory write command when a 128-byte boundary is crossed, the transfer will continue.
3.2.1.4 PCI-X to PCI-X Transactions
When both buses are operating in the PCI-X mode, the bridge passes the memory write command that it
receives to the destination interface along with the originating byte count and transaction ID.
The bridge attempts to transfer a memory write command when the transaction ends or a 128-byte boundary
is crossed, whichever comes first. As long as a 128-byte buffer is full or the end of transfer remains from the
PCI-X memory write command when a 128-byte boundary is crossed, the transfer will continue.
If a transaction is disconnected on the destination interface in the middle of a continuing transfer, the byte
count and address are updated and the transaction is presented again on the destination interface. If a trans-
action is disconnected in the middle of a continuing transfer on the originating interface, the originator must
present the transaction again with the updated byte count and address.
3.2.2 Delayed/Split Write Transactions
I/O writes, Type 1 configuration writes, and Type 0 configuration writes on the secondary bus are treated as
delayed transactions in the bridge. These commands are retried on the originating bus, completed on the
destination bus if necessary, and then completed on the originating bus. The bridge executes DWord transac-
tions only as delayed transactions in the conventional PCI mode and as split requests in PCI-X mode.
There is only one request queue entry for either delayed or split write transactions.
3.2.3 Immediate Write Transactions
Type 0 configuration writes on the primary PCI interface meant for the bridge are treated as an immediate
write transaction by the bridge. The bridge executes the transaction and indicates its completion by accepting
the DWord of data immediately.
3.3 Read Transactions
Read transactions are treated as either delayed (PCI), split (PCI-X), or immediate read transactions, as
shown in
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