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| 型號(hào)： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 56/144頁 |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_intro.fm.01
October 15, 2001
General Information
Page 19 of 144
amount of space assigned to each transaction is dynamic. A single transaction can utilize from one to eight
128-byte subsections as needed. Each posted write queue is an 8-entry FIFO, providing up to eight active
write transactions in each direction. Activity generally occurs when a 128-byte segment is filled or emptied,
this keeps data flowing by re-using 128-byte subsections as they become available.
2.5.2.3 Single Data Phase Buffers
There is one single data phase buffer for each direction to hold read or write data from 4-byte split or delayed
transactions. These transactions include all I/O or configuration operations as well as doubleword memory
read operations.
2.5.3 Address Decoding
The IBM 133 PCI-X Bridge R2.0 is a transparent bridge and uses a flat addressing model. Both the PCI and
PCI-X address spaces are split between the primary bus and the secondary bus. Address ranges residing on
the secondary bus are defined by the I/O, memory, prefetchable memory base and limit, and the optional
base address registers 0 and 1 in the bridge configuration space. All other addresses are assumed to reside
on the primary bus. Inverse address decoding is used to determine when to forward transactions upstream.
The only exception to this is when the optional opaque address range is enabled and defined by its base and
limit registers. The IBM 133 PCI-X Bridge R2.0 does not recognize transactions for addresses within the
opaque range on either bus. This region may be used, for example, for peer-to-peer communication between
devices on the secondary bus.
The IBM 133 PCI-X Bridge R2.0 supports full 64-bit addressing and handles dual address cycles on both
interfaces. The device provides no capability for translating addresses.
The bridge configuration registers are accessible from either the primary or secondary interface through Type
0 configuration reads and writes. On the secondary interface, the bridge claims Type 1 configuration write
transactions that specify conversion to a special cycle on an upstream bus segment.
2.5.4 Bus Arbitration
The IBM 133 PCI-X Bridge R2.0 contains an arbiter for the secondary interface that is enabled or disabled via
an input signal pin. It provides bus arbitration for up to six additional masters, each of which may be assigned
high or low priority or may be masked off. When the internal arbiter is being used and the IBM 133 PCI-X
Bridge R2.0 request is not masked off, the bus will be parked at the bridge whenever there are no pending
requests.
The arbiter implements a two-level fairness algorithm that allows each device within a level to receive grant
requests cyclically. The arbiter uses the arbitration priority register to determine which agents are high priority
(HP) devices and which are low priority (LP) devices. At different points in time, snapshots are taken of all
pending requests for each priority level. All captured HP requests are serviced first, then one of the captured
LP requests is serviced. At this point, a new HP snapshot is taken, picking up any new HP requests. All
captured HP requests are serviced before continuing with the next LP request still pending from the previous
LP snapshot. A new snapshot of pending LP requests is taken only after all requests from the previous LP
snapshot have been serviced.
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