參數(shù)資料
型號： IBM21P100BGC
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA304
封裝： 31 X 31 MM, PLASTIC, BGA-304
文件頁數(shù)： 14/144頁
文件大?。?/td> 5197K
代理商： IBM21P100BGC
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Signal Descriptions
Page 110 of 144
ppb20_signals.fm.01
October 15, 2001
P_LOCK#
I
1
Lock
Indicates that an atomic (unbroken) operation is required that may need multiple primary
bus transactions to complete.
P_LOCK# is monitored by the bridge when serving as the selected primary bus target in
order to detect exclusive access.
P_PAR
I/O
1
Parity
Parity protection bit for the lower half of the address/data and command/byte enable
buses on the primary interface. It provides even parity across P_AD(31:00) and
P_C/BE(3:0)#.
P_PAR64
I/O
1
Parity Upper DWord
Parity protection bit for the upper half of the address/data and command/byte enable
buses on the primary interface. It provides even parity across P_AD(63:32) and
P_C/BE(7:4)#.
P_PERR#
I/O
1
Parity Error
Used to report data parity errors on the primary interface.
P_PERR# is monitored by the bridge when performing a primary bus write transaction
on behalf of a secondary bus master or when serving as the selected slave for a primary
bus read transaction.
P_PERR# is driven by the bridge when performing a primary bus read transaction on
behalf of a secondary bus master or when serving as the selected slave during a pri-
mary bus write transaction.
P_REQ#
O
1
Request
Driven by the bridge to request use of the primary bus.
P_REQ64#
I/O
1
Request 64-Bit Transfer
When asserted by the current master on the primary bus, this signal indicates a desire
to transfer data using 64 bits.
P_RST#
I
1
Primary Bus Reset
This signal is used to:
Initialize thebridgetoa knownstate,
Drive the Secondary Bus Reset signal (S_RST#), and
Drive all primary bus and secondary bus output signals to their benign state.
P_SERR#
O
1
System Error
This signal is used to report address parity errors and other system errors where the
results will be catastrophic.
P_SERR# is driven by the bridge when detecting such errors on the primary bus or in
the case of an error in which the initiator of the transaction cannot be otherwise notified.
It is also driven as the result of S_SERR# being asserted on the secondary bus.
P_STOP#
I/O
1
Stop
Indicates that the current target is requesting that the initiator stop the current transac-
tion on the primary bus.
P_STOP# is monitored by the bridge when performing a primary bus transaction on
behalf of a secondary bus master.
P_STOP# is driven by the bridge when addressed as a target and is asserted low to
indicate target termination.
P_TRDY#
I/O
1
Target Ready
Indicates the ability of the target on the primary bus to complete the current data phase
of the transaction. It is used in conjunction with the P_IRDY# signal.
P_TRDY# is monitored by the bridge when performing a primary bus transaction on
behalf of a secondary bus master.
P_TRDY# is driven by the bridge when a primary bus master is performing a transaction
in which the bridge is the selected target.
Total
89
Table 7-1. Primary Interface Signal List (Page2of 2)
Signal Name
I/O
Width
Description
相關(guān)PDF資料
PDF描述
IBM25403GCX-3JC76C2 RISC PROCESSOR, PQFP16
IBM25405GP-3BA200C2 RISC PROCESSOR, PBGA456
IBM25EMPPC603EFG-100 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240
IBM25EMPPC603EBG-100 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255
IBM25EMPPC740LDBC4000 32-BIT, 400 MHz, RISC PROCESSOR, CBGA255
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IBM24L5086 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述:
IBM25403GCX-3BC80C2 制造商:IBM 功能描述:RISC PROCESSOR, 160 Pin Plastic BGA
IBM25403GCX-3JC50C2 制造商:IBM 功能描述:403GCX-3JC50C2
IBM25403GCX-3JC66C2 制造商:IBM 功能描述:
IBM25403GCX3JC76C2 制造商:IBM 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*