參數(shù)資料
型號(hào): IBM21P100BGC
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA304
封裝: 31 X 31 MM, PLASTIC, BGA-304
文件頁數(shù): 75/144頁
文件大?。?/td> 5197K
代理商: IBM21P100BGC
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Configuration Registers
Page 36 of 144
ppb20_pcix_regs.fm.01
October 15, 2001
- Revision ID
- Class Code
- Cache Line Size
- Latency Timer
- Header Type
- Built-in Self Test (BIST)
The remaining 48 bytes are the PCI Device Header Type region with registers for:
- Base Address Registers
- Primary Bus Number
- Secondary Bus Number
- Subordinate Bus Number
- Secondary Latency Timer
- I/O Base and Limit
- Secondary Status
- Memory Base and Limit
- Prefetchable Memory Base and Limit
- Prefetchable Base and Limit Upper 32 Bits
- I/O Base and Limit Upper 16 Bits
- Capabilities Pointer
- Expansion ROM Addresses
- Interrupt Line
- Interrupt Pin
- Bridge Control
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