參數(shù)資料
型號: IBM21P100BGC
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA304
封裝: 31 X 31 MM, PLASTIC, BGA-304
文件頁數(shù): 124/144頁
文件大?。?/td> 5197K
代理商: IBM21P100BGC
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Configuration Registers
Page 80 of 144
ppb20_pcix_regs.fm.01
October 15, 2001
5.2.5.13 Opaque Memory Base Register
This register specifies base address bits 31:20 of the opaque memory address range. It is used in conjunction
with the opaque memory limit register, the opaque memory base upper 32 bits register, and the opaque
memory limit upper 32 bits register to specify a range of 64-bit memory addresses that are used exclusively
on the secondary bus. These memory addresses will not be accepted by the bridge on the primary or the
secondary buses. This address range is enabled by bit 0 of the opaque memory enable register. Bits 19:0 of
the base address are assumed to be x‘0 0000’. This register also specifies that the bridge supports 64-bit
opaque memory addressing.
Address Offset
x‘74’
Access
See individual fields
Reset Value
x‘0001’
Opaque Memory Base Address
64-bit
addressing
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
FieldNameand Description
15:4
RW
Opaque Memory Base Address
Address bits 31:20 of the base address for the opaque memory address range. Memory operations in this
range are not accepted by the bridge on either the primary or secondary interfaces.
3:0
RO
64-bit addressing
Set to b‘0001’ to indicate support of 64-bit addressing.
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