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參數(shù)資料
| 型號： | IBM25405GP-3BA200C2 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, PBGA456 |
| 封裝： | PLASTIC, BGA-456 |
| 文件頁數(shù)： | 1/48頁 |
| 文件大小： | 649K |
| 代理商： | IBM25405GP-3BA200C2 |
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PowerPC 405GP Embedded Controller
Advance Information
Data Sheet
galdsh5f
06/15/99 Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 48
Features
PowerPCTM 405 core operating up to 200 MHz
PC-100 Synchronous DRAM interface operating
up to 100 MHz
32-bit interface for non-ECC applications
40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
External Peripheral Bus
Flash ROM/Boot ROM interface
Direct support for 8-, 16-, or 32-bit SRAM
and external peripherals
Up to eight devices
External Mastering supported
DMA support for external peripherals, internal
UART and memory
Scatter-gather chaining supported.
Four channels
PCI Revision 2.2 Compliant Interface (32-bit, up
to 66 MHz).
PCI Bus interface may be congured to
operate synchronously or asynchronously
to the chip input clock
Internal PCI Bus Arbiter which may be dis-
abled for use with an external arbiter
Ethernet 10/100Mbps (full-duplex) support
Medium Independent Interface (MII)
Programmable Interrupt Controller supports
interrupts from a variety of sources
Supports 7 external and 17 internal
interrupts
Edge triggered or level-sensitive
Positive or negative active
Non-critical or critical interrupt to 405
processor core
Programmable critical interrupt priority
ordering
Programmable critical interrupt vector for
faster vector processing
Programmable Timers
Two serial ports (16550 compatible UART)
One IIC (I2C) interface
General Purpose I/O (GPIO) available
Supports JTAG for board level testing
Internal PLB bus runs at SDRAM interface fre-
quency, up to 100MHz maximum
Supports PowerPC processor boot from PCI
memory
Description
Designed specifically to address embedded applica-
tions, the 405GP provides a high-performance, low-
power solution that interfaces to a wide range of
peripherals by incorporating on-chip power man-
agement features and intrinsically lower power dis-
sipation requirements.
This chip contains a high-performance RISC pro-
cessor core, SDRAM controller, PCI bus interface,
Ethernet interface, control for external ROM and
peripherals, DMA with scatter-gather support, serial
ports, I2C interface, and general purpose I/O.
Technology: IBM CMOS SA12E 0.25
m
(0.18
m L
eff)
Package: 456-ball enhanced PBGA
Power: Less than 2.5 W (estimated)
.
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