參數(shù)資料
型號(hào)： IBM25405GP-3BA200C2
元件分類(lèi)： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA456
封裝： PLASTIC, BGA-456
文件頁(yè)數(shù)： 34/48頁(yè)
文件大?。?/td> 649K
代理商： IBM25405GP-3BA200C2
PowerPC 405GP Embedded Controller
Data Sheet
Advance Information
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 48
galdsh5f
06/15/99 Preliminary
The PPC405GP is designed using the IBM Microelectronics Blue LogicTM methodology in which major func-
tional blocks are integrated together to create an application-specic ASIC product. This approach provides a
consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
Note: IBM CoreConnect busses provide:
64-bit PLB interfaces up to 100MHz
32-bit OPB interfaces up to 50MHz
Address Map Support
The 405GP incorporates two simple and separate address maps. The rst is a xed processor address map
that serves the PowerPC family of processors. This address map denes the possible contents of various
address regions which the processor may access. The second address map is for Device Conguration Reg-
isters (DCR). This address map is accessed by software running on the PPC405 processor through the use
of MTDCR and MFDCR commands.
PPC405GP Embedded Controller Functional Block Diagram
PPC405GP
Processor Core
DOCM
IOCM
DCU
ICU
OCM
Control
OCM
SRAM
DCR Bus
16KB
On-chip Peripheral Bus (OPB)
GPIO
I2C
UART
MAL
Ethernet
DMA
Bridge
Processor Local Bus (PLB)
SDRAM
PCI Bridge
Code
Decompression
SRAM/ROM
Peripheral
Controller
Clock
Control
Reset
Power
Mgmt
JTAG
Trace
Timers
MMU
MII
Controller
OPB
Interrupt
Controller
Arb
50 MHz max
- 32-bit addr
- 32-bit data
100 MHz max
- 13-bit addr
- 32-bit data
External
Bus Master
Controller
Universal
I-Cache
8KB
D-Cache
(4-Channel)
(CodePack
)
66 MHz max
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