參數(shù)資料
型號: IBM25405GP-3BA200C2
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA456
封裝: PLASTIC, BGA-456
文件頁數(shù): 40/48頁
文件大小: 649K
代理商: IBM25405GP-3BA200C2
PowerPC 405GP Embedded Controller
Advance Information
Data Sheet
galdsh5f
06/15/99 Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 45 of 48
UART0_DTR
12
8
UART0_RI
12
8
UART0_RTS
12
8
UART0_Rx
12
8
UART0_Tx
12
8
UART1 _RTS
[UART1_DTR]
12
8
UART1_DSR
[UART1_CTS]
n/a
UART1_Rx
n/a
UART1_Tx
12
8
UARTSerClk
n/a
Interrupts Interface
IRQ0:6[GPIO17:23]
12
8
JTAG Interface
TCK
n/a
async
TDI
n/a
async
TDO
12
8
async
TMS
n/a
async
TRST
n/a
async
System Interface
DrvrInh1:2
n/a
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]
12
8
Halt
dc
n/a
async
RcvrInh
n/a
SysClk
n/a
SysErr
12
8
async
SysReset
12
8
async
TestEn
n/a
async
TmrClk
n/a
async
I/O Specications (Part 3 of 3)
Notes:
1. SDRAM command interface is a two-cycle path (first driven in cycle 1 and then sampled at SDRAMs in cycle 2)
2. Output timings are actually relative to a rising edge of the internal PLB bus clock, which is always an integer multiple of
SysClk. The on chip PLL maintains this internal clock such that it is rising edge aligned with SysClk. For this reason all
SDRAM output timings are shown relative to SysClk.
3. Asynchronous PCI timings at 66MHz maximum
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(minimum)
Hold Time
(minimum)
Valid Delay
(maximum)
50pF load
Hold Time
(minimum)
50 pF load
I/O H
(maximum)
I/O L
(minimum)
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