參數(shù)資料
型號(hào)： IBM25405GP-3BA200C2
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA456
封裝： PLASTIC, BGA-456
文件頁數(shù)： 19/48頁
文件大?。?/td> 649K
代理商： IBM25405GP-3BA200C2
PowerPC 405GP Embedded Controller
Data Sheet
Advance Information
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 26 of 48
galdsh5f
06/15/99 Preliminary
Ethernet Interface (Number of pins = 18)
AD20
AC20
AF23
AE23
PHYRxD3
PHYRxD2
PHYRxD1
PHYRxD0
Received data. This is a nibble wide bus from
the PHY. The data is synchronous with the
PhyRxClk.
I
5V tolerant
3.3V Rcvr
n/a
A
1, 4
P25
L24
L25
J26
EMCTxD3
EMCTxD2
EMCTxD1
EMCTxD0
Transmit data. A nibble wide data bus towards
the net. The data is synchronous to the
PHYTxClk.
O
5V tolerant
3.3V LVTTL
50
A
6
U24
PHYRxErr
Receive Error. This signal comes from the
PHY and is synchronous to the PHYRxClk.
I
5V tolerant
3.3V LVTTL
Rcvr
n/a
A
1, 5
AF20
PHYRxClk
Receiver Medium clock. This signal is
generated by the PHY.
I
5V tolerant
3.3V LVTTL
Rcvr
n/a
A
1, 4
V24
PHYRxDV
Receive Data Valid. Data on the Data Bus is
valid when this signal is activated. Deassertion
of this signal indicates end of the frame
reception.
I
5V tolerant
3.3V LVTTL
Rcvr
n/a
A
1, 5
W23
PHYCrS
Carrier Sense signal from the PHY. This is an
asynchronous signal.
I
5V tolerant
3.3V LVTTL
Rcvr
n/a
A
1, 5
K25
EMCTxErr
Transmit Error. This signal is generated by the
Ethernet controller and is connected to the
PHY. This signal informs the PHY that an error
was detected. This signal is synchronous to
the PHYTxClk.
O
5V tolerant
3.3V LVTTL
50
A
6
K23
EMCTxEn
Transmit data Enabled. This signal is driven by
EMAC2 to the PHY. Data is valid during the
active state of this signal. Deassertion of this
signal indicates end of frame transmission.
This signal is synchronous to the PHYTxClk.
O
5V tolerant
3.3V LVTTL
50
A
6
E25
PHYTxClk
This clock comes from the PHY and is the
Medium Transmit clock
I
5V tolerant
3V LVTTL
Rcvr
n/a
A
1, 4
AA25
PHYCol
Collision signal from the PHY. This is an
asynchronous signal
I
5V tolerant
3.3V LVTTL
Rcvr
n/a
A
1, 5
H24
EMCMDClk
Management Data Clock. The MDClk is
sourced to the PHY. This clock has a period of
400ns, adjustable via the FMO_DIV_CLK
register, with no maximum high or low times.
Management information is transferred
synchronously with respect to this clock.
Ot
5V tolerant
3.3V LVTTL
50
A
Pin Functional Description 35mm, 456-Ball Enhanced Plastic Ball Grid Array Package (Part 3 of 14)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k to 5V)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input, pull-up or pull-down required
Ball
Signal Name
Description
I/O
Type
Imped
ance
(
)
BHC
Notes
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