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參數(shù)資料
| 型號： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 13/144頁 |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_preface.fm.01
October 15, 2001
Preface
Page 11 of 144
1. Preface
1.1 About This Book
This book describes the features and operation of the IBM 133 PCI-X Bridge R2.0. While every effort has
been made to ensure that all information contained herein is as accurate as possible, users of this document
should be aware that it is subject to change by IBM without notice. Any comments, corrections, and recom-
mended additions to improve this book may be forwarded to the address inside the front cover.
1.2 Who Should Read This Manual
This document is designed for engineers and system designers interested in implementing PCI-X capable
systems or adapters using a PCI-X to PCI-X transparent bridge device.
It is assumed that the reader is acquainted with the PCI and PCI-X bus specifications. For details about bus
protocols and general bridge architecture, see the documents listed in
1.3 Document Contents
1.4 Conventions and Notation
Throughout this document, bit notation is non-IBM, meaning that bits and bytes are numbered in descending
order from left to right. Thus, for a four-byte word, bit 31 is the most significant bit and bit zero is the least
significant bit.
Chapter
Description
1.
Document conventions, audience, references, and terminology
2.
Architectural overview with highlights of the features and functions of the IBM 133 PCI-X Bridge
R2.0 as well as a functional block diagram
3.
Detailed description of the operation of the device in its various supported modes
4.
Description of the ordering rules that control the forwarding of transactions across the bridge
5.
An explanation of the configuration registers and programming interface for the device
6.
Clocking requirements, reset functions, and related parameters
7.
A list of device signals and descriptions of the their use
8.
The signal-to-package pin assignment list
9.
The mapping of the device I/Os to bits in the JTAG Boundary Scan Ring
10.
Electrical specifications for the device
11.
Mechanical and thermal specifications for the device
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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