參數(shù)資料
型號(hào): IBM21P100BGC
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA304
封裝: 31 X 31 MM, PLASTIC, BGA-304
文件頁數(shù): 129/144頁
文件大?。?/td> 5197K
代理商: IBM21P100BGC
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_pcix_regs.fm.01
October 15, 2001
Configuration Registers
Page 85 of 144
4
RW
Split Completion Overrun
This bit is set if the bridge terminates a split completion on the secondary bus with retry or disconnect at next
ADB because the bridge buffers are full. It is used by algorithms that optimize the setting of the downstream
split transaction commitment limit register.
0
The bridge has accepted all split completions.
1
The bridge has terminated a split completion with retry or disconnect at next ADB because the
bridge buffers were full.
3
RW
Unexpected Split Completion
This bit is set if an unexpected split completion with a requester ID equal to the bridge’s secondary bus num-
ber, device number x‘00’, and function number 0 is received on the bridge’s secondary interface.
0
No unexpected split completion has been received.
1
An unexpected split completion has been received.
2
RW
Split Completion Discarded
This bit is set if the bridge discards a split completion moving toward the secondary bus because the
requester would not accept it.
0
No split completion has been discarded.
1
A split completion has been discarded.
1
RO
133 MHz Capable
This bit is read-only and is a b‘1’ indicating that this bridge is capable of 133 MHz operation on the second-
ary interface.
0
RO
64-bit Device
This bit is read-only and is a b‘1’ indicating that the width of the bridge’s secondary AD interface is 64 bits.
Bit(s)
Access
Field Name and Description
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