- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67681 > IBM21P100BGC PCI BUS CONTROLLER, PBGA304 PDF資料下載
參數(shù)資料
| 型號(hào)： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 144/144頁 |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁當(dāng)前第144頁
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_clock_reset.fm.01
October 15, 2001
Clocking and Reset
Page 99 of 144
6. Clocking and Reset
This section explains the clocking requirements and reset functions of the IBM 133 PCI-X Bridge R2.0.
6.1 Clocking Domains
The IBM 133 PCI-X Bridge R2.0 has two clocking domains, one for the primary interface and one for the
secondary interface. Each interface has its own clock input pin. The primary interface is controlled by the
P_CLK input. The secondary interface and the internal arbiter are controlled by the S_CLK input. The bridge
does not supply the clocks on either interface. The two bus clocks may be run synchronously or asynchro-
nously to one another. The two clock frequencies are independent of each other and each may have any
value allowed by the PCI/PCI-X bus architectures. A spread spectrum clock input is supported for either or
both interfaces within the architectural bounds.
The bridge contains a separate internal phase-locked loop (PLL) circuit for each clocking domain. The PLL for
each interface is employed when its bus is running in the PCI-X mode, as determined by the bus initialization
process described below. When either bus is running in the PCI mode, the respective PLL is bypassed to
allow for any clock frequency from zero to 66 MHz.
6.2 Clock Jitter
Clock jitter is defined as the relationship of one clock edge to a subsequent clock edge, measured at the
same point. If these two edges are separated by one clock cycle, it is called cycle-to-cycle or short term jitter.
If they are separated by hundreds or thousands of cycles, it is called long term jitter. As specified in
Information on page 139, the IBM 133 PCI-X Bridge R2.0 tolerates a maximum of ± 250 ps of short term and
long term jitter on each of its clock inputs. Clock jitter introduced by the internal PLLs of the bridge is
accounted for within this maximum specification.
Careful design of the clock generation circuitry is an important factor in determining the speed of the bus. As
indicated in the PCI and PCI-X architectures, all sources of clock jitter must be considered when determining
the bus clock frequency. The minimum and maximum clock period specifications must not be violated for any
single clock cycle. The system clock output period, including all sources of clock period variation such as jitter
and component tolerances, must always be within the minimum and maximum limits defined for the mode in
which the bus is configured. For example, if a specific system clock design has a maximum clock period vari-
ation of 180 ps, then the nominal clock period for the PCI-X 133 range needs to be at least 7.68ns (7.5ns +
0.180ns), making the maximum frequency allowed for this case is just over 130 MHz.
6.3 Mode and Clock Frequency Determination
As explained in Sections 6.2 and 8.9 of the
PCI-X Addendum to the PCI Local Bus Specification, the mode
and frequency range of each bus is determined by the values on its M66EN and PCIXCAP signals when the
bus reset signal is active. Each bus client is then informed of the determination via an initialization pattern that
is broadcast at the de-assertion or rising edge of the reset signal. This process is accomplished on the
secondary interface differently than on the primary interface, due to architectural requirements for PCI-X
bridges. The details for each are given below.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM25403GCX-3JC76C2 | RISC PROCESSOR, PQFP16 |
| IBM25405GP-3BA200C2 | RISC PROCESSOR, PBGA456 |
| IBM25EMPPC603EFG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240 |
| IBM25EMPPC603EBG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| IBM25EMPPC740LDBC4000 | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA255 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM24L5086 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM25403GCX-3BC80C2 | 制造商:IBM 功能描述:RISC PROCESSOR, 160 Pin Plastic BGA |
| IBM25403GCX-3JC50C2 | 制造商:IBM 功能描述:403GCX-3JC50C2 |
| IBM25403GCX-3JC66C2 | 制造商:IBM 功能描述: |
| IBM25403GCX3JC76C2 | 制造商:IBM 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。