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參數(shù)資料
| 型號： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 53/144頁 |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
General Information
Page 16 of 144
ppb20_intro.fm.01
October 15, 2001
2.2 Description
The IBM 133 PCI-X Bridge R2.0 transparently connects two electrically separate PCI-X bus domains,
allowing concurrent operations on both buses. This results in good utilization of the buses in various system
configurations and enables hierarchical expansion of I/O bus structures.
As described by the PCI-X architecture, the IBM 133 PCI-X Bridge R2.0 is capable of handling 64-bit data at
a maximum bus frequency of 133 MHz (depending upon the bus topology and load) and is backward compat-
ible with all 3.3V I/O conventional PCI interfaces.
The IBM 133 PCI-X Bridge R2.0 also provides extensive buffering and prefetching mechanisms for efficient
transfer of data through the device, facilitating multi-threaded operation and high system throughput.
2.3 Technology Highlights
The IBM 133 PCI-X Bridge R2.0 is implemented using IBM’s CMOS 6SF technology, which is a 0.25 micron
(
m) lithography process with a 0.18 mLeffective. The device requires two power supplies, one at 2.5 V for
internal logic and the other at 3.3 V to power the device I/O circuits. The device is packaged in a 31mm ther-
mally and electrically enhanced plastic ball grid array (H-PBGA) with 304 balls. See the
on page 139 and the
Mechanical Information on page 141 for further details.
2.4 Block Diagram
The IBM 133 PCI-X Bridge R2.0 is composed of the following major functional blocks as shown in
Two PCI-X interface macros, one of the elements in the IBM Blue Logic Core Library. Each macro han-
dles the PCI/PCI-X protocol for its respective bus and depending on the type of transaction, can act as
either a bus master or a bus slave. These macros transfer data and control information flowing to and
from the blocks shown in the middle of the diagram.
Two phase-locked loops (PLLs), one for the primary clock domain and one for the secondary clock
domain. The PLL for each clock domain is used when that bus is running in PCI-X mode; in PCI mode,
the PLL is bypassed to allow the full frequency range as defined by the bus architecture. The two bus
clocks may be run synchronously or asynchronously. A spread-spectrum clock input, within the architec-
tural bounds, is supported for either or both interfaces.
One set of configuration registers, programmable either from the primary or secondary interface. The first
64 bytes of this address space conform to the architectural format for bridge devices, called Header Type
1. The remaining 192 bytes are device-specific registers. Each register is fully defined in
Two data/control units, one for downstream transactions and one for upstream transactions. These sym-
metric units each contain separate buffers for burst read, posted write, and single data phase operations.
Read and write queues, queue compare logic, address decoding, control logic, and other control func-
tions are also included in these blocks.
An arbiter for the secondary bus, which can be disabled if an external arbiter is employed. When enabled,
bus arbitration is provided for the IBM 133 PCI-X Bridge R2.0 and up to six other masters. Each client can
be assigned high or low priority, or can be masked off.
A clocking and reset control unit to manage these common device functions.
A JTAG controller, compliant with IEEE Standard 1149.1, to facilitate boundary scan testing.
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