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參數資料
| 型號： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數： | 30/144頁 |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_jtag.fm.01
October 15, 2001
JTAG Boundary Scan
Page 125 of 144
9. JTAG Boundary Scan
The IBM 133 PCI-X Bridge R2.0 provides a JTAG test port that is compliant with IEEE Standard 1149.1,
IEEE
Standard Test Access Port and Boundary-Scan Architecture, to facilitate card and board testing using
boundary-scan techniques. This function consists of the following major components:
the five signal test port interface with the signals JTG_TCK, JTG_TDI, JTG_TDO, JTG_TMS, and
JTG_TRST# (see
Signal Descriptions on page 109 for further details on these signals);
the test access port (TAP) controller;
the instruction register (IR) and its associated instruction decoder;
the bypass register;
a device ID register, and
the boundary-scan register.
The JTAG test port is intended to be used only while the bridge is not operating in a functional mode.
The information presented in this section is available in a standardized, soft-copy format called a boundary
scan description language (BSDL) file. Contact your IBM sales representative for further information.
9.1 TAP Controller Initialization
After power-up of the IBM 133 PCI-X Bridge R2.0 device, the TAP Controller must be put into its test-logic-
reset state to disable the JTAG logic and allow the bridge to function normally. This may be done by driving
the JTG_TMS signal high and pulsing the JTG_TCK signal five or more times or by asserting the
JTG_TRST# signal. If the bridge will not be connected into a boundary scan ring, the JTG_TRST# signal may
be tied directly to GND.
9.2 Instruction Register and Codes
The IBM 133 PCI-X Bridge R2.0 implements a 4-bit Instruction register to control the operation of the JTAG
logic. The defined instruction codes are shown in
Table 9-1. Those bit combinations that are not listed are
equivalent to the BYPASS (b‘1111’) instruction:
Table 9-1. JTAG Logic Instruction Codes
Instruction Code
Instruction Name
Register Selected
Operation
b‘0000’
EXTEST
Boundary-Scan
Drives / receives off-chip test data
b‘0100’
SAMPLE
Boundary-Scan
Samples inputs / pre-loads outputs
b‘0101’
HIGHZ
Bypass
Tri-states outputs
b‘0110’
IDCODE
Device ID
Accesses the Device ID register, to read manufac-
turer ID, part number, and version number
b‘1111’
BYPASS
Bypass
SelectsBypassregister
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