參數(shù)資料
型號： IBM21P100BGC
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA304
封裝： 31 X 31 MM, PLASTIC, BGA-304
文件頁數(shù)： 63/144頁
文件大?。?/td> 5197K
代理商： IBM21P100BGC
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_operations.fm.01
October 15, 2001
Bus Operation
Page 25 of 144
3.3.1 Memory Read Transactions
The conventional PCI memory-read, memory-read-line, memory-read-multiple, PCI-X memory-read-DWord,
and PCI-X memory-read-block transactions are used to transfer memory data from the originating side of the
bridge to the destination side of the bridge. All memory read transactions are either delayed or split on the
originating interface depending on the mode of the originating interface.
3.3.1.1 PCI to PCI-X Transactions
The IBM 133 PCI-X Bridge R2.0 must translate the conventional memory read command to either the
memory read DWord or the memory read block PCI-X Command. If the conventional memory read command
targets non-prefetchable memory space, the command is translated into a memory read DWord. In any other
instance the conventional memory read command gets translated into a memory read block PCI-X command.
The prefetching algorithm for the conventional memory read command in the prefetchable space is controlled
by bits 9:8 of the primary and secondary data buffering control registers. The default value of these bits indi-
cates that one cache line will be prefetched.
The bridge must translate the conventional memory read line command to the memory read block PCI-X
command. The prefetching algorithm is controlled by bits 7:6 of the primary and secondary data buffering
control registers. The default value of these bits indicates that one cache line will be prefetched.
The bridge must translate the conventional memory read multiple command to the memory read block PCI-X
command. The prefetching algorithm is controlled by bits 5:4 of the primary and secondary data buffering
control registers. The default value of these bits indicates that a full prefetch will be done, subject to the limit
imposed by the maximum memory read byte count value set by bits (14:12) of the same register. The default
value for this field is 512 bytes or an entire read buffer. Using a value greater than this is possible, but it may
be constrained by the setting of the split transaction commitment limit value in the upstream or downstream
split transaction register, since the target bus is in PCI-X mode. Data fetching operations will be disconnected
at all 1MB boundaries.
3.3.1.2 PCI-X to PCI Transactions
The IBM 133 PCI-X Bridge R2.0 translates PCI-X memory read DWord commands into conventional memory
read commands.
Table 3-4. Read Transaction Handling
Type of Transaction
Type of Handling
Memory Read
Delayed
Memory Read Line
Delayed
Memory Read Multiple
Delayed
Memory Read DWord (PCI-X)
Split (PCI-X)
Memory Read Block (PCI-X)
Split (PCI-X)
I/O Read
Delayed/Split (PCI-X)
Type 0 Configuration Read
Immediate on the primary bus, Delayed/Split (PCI-X) on the sec-
ondary bus
Type 1 Configuration Read
Delayed/Split (PCI-X)
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