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| 型號(hào)： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 6/144頁(yè) |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_clock_reset.fm.01
October 15, 2001
Clocking and Reset
Page 103 of 144
Note that the values on these inputs are only valid at reset time; they may not be used to change the driver
mode dynamically, though they may be set differently at each reset if desired to account for changes in bus
loading and mode. Regardless of the driver impedance used, signal analysis should always be done with the
actual or expected bus topology and wiring to verify proper operation. Nets may need to be tuned and series
terminations or other adjustments may be required in order to meet the frequency targets.
6.6 Reset Functions and Operations
Each bus interface has an asynchronous bus reset signal that is used at power-on and other times to place
the IBM 133 PCI-X Bridge R2.0 into a known state. On the primary interface, the reset signal is an input to the
bridge. On the secondary interface, the reset signal is an output driven by the bridge in its role as the central
resource for that bus.
6.6.1 Primary Reset
The bus reset for the primary interface is called P_RST#. It is an input to the bridge and is controlled by an
external upstream central resource. When asserted (see
Figure 6-2 and Table 6-2) it forces all bus output
signals from the bridge into their benign states and sets all configuration registers within the bridge to their
reset values as defined in
Configuration Transactions on page 28. Activating the P_RST# signal also causes
the secondary bus reset signal to be asserted, as required by the PCI/PCI-X specifications.
On the de-assertion or rising edge of the P_RST# signal, the initialization pattern is received off of the bus
and latched into the bridge. If the indication is that the primary bus is operating in the PCI-X mode, an internal
PLL is used to source the clock tree for the primary clock domain. The appropriate range and tuning bits for
the PLL are set according to the indicated frequency range, and an internal PLL reset signal is deactivated to
allow the PLL to begin locking to the P_CLK input frequency. Since the PLL requires an allowance of 100
s
to accomplish this frequency lock, an internal reset is held on the logic in the primary clock domain until this
time period has elapsed. While the internal logic reset is active, the bridge will not respond to any primary bus
transactions. When the primary bus is operating in the PCI mode, the internal PLL for the primary interface is
not used. In this case, the internal PLL reset remains activated, keeping the PLL in the bypass mode, and the
internal logic reset is held for only seven additional primary clock cycles after the rising edge of P_RST#.
6.6.2 Secondary Reset
The bus reset for the secondary interface is called S_RST#, it is an output from the bridge. Whenever
P_RST# is asserted or when the secondary bus reset bit (bit 6) of the bridge control register is set to b’1’,
S_RST# is asserted immediately, asychronously to the secondary bus clock. When the secondary bus reset
bit is being used to control S_RST#, the software must be sure that the required minimum reset active time
(Trst)of 1 ms is met.
Several things must occur at or prior to the de-assertion of the secondary bus reset signal. Once P_RST# is
de-asserted or the secondary bus reset bit is changed from b’1’ to b’0’, indicating that S_RST# should be
deactivated, the bridge will wait for the S_CLK_STABLE signal to be asserted before proceeding. The S_CLK
input must be stable at a frequency within the bus capability limits prior to the assertion of S_CLK_STABLE.
Since the
PCI Local Bus Specification requires that the bus clock be stable for at least 100
sprior to the
de-assertion of the bus reset, S_CLK_STABLE serves as a gate to a timer that ensures that this requirement
is met. During this time delay period, the determination of the secondary bus mode and frequency capability
is made through the use of the programmable pull-up circuit described in
Section 6.3.2. This process may
include upto80
s for the capacitive load on the S_PCIXCAP net to be charged, making it prudent to overlap
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