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| 型號： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 130/144頁 |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Configuration Registers
Page 86 of 144
ppb20_pcix_regs.fm.01
October 15, 2001
5.2.5.20 PCI-X Bridge Status Register
This register identifies the capabilities and current operating mode of the bridge on its primary bus.
Address Offset
x‘84’
Access
See individual bit descriptions. Reads to this register behave normally. Writes are
slightly different in that bits can be reset, but not set. A bit is reset whenever the
register is written, and the data in the corresponding bit location is a ‘1’.
Reset Value
x‘0003 00F8’
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
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2
1
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Bit(s)
Access
Field Name and Description
31:22
RO
Reserved
21
RW
Split Request Delayed
This bit is set any time the bridge has a request to forward a transaction to the primary bus, but cannot because
there is not enough room within the limit specified in the split transaction commitment limit field in the upstream
split transaction control register. It is used by algorithms that optimize the setting of the upstream split transac-
tion commitment limit register.
0
The bridge has not delayed a split request.
1
The bridge has delayed a split request.
20
RW
Split Completion Overrun
This bit is set if the bridge terminates a Split Completion on the primary bus with retry or disconnect at next
ADB because the bridge buffers are full. It is used by algorithms that optimize the setting of the upstream split
transaction commitment limit register.
0
The bridge has accepted all split completions.
1
The bridge has terminated a split completion with retry or disconnect at next ADB because the bridge
buffers were full.
19
RW
Unexpected Split Completion
This bit is set if an unexpected split completion with a requester ID equal to the bridge’s primary bus number,
device number, and function number is received on the bridge’s primary interface.
0
No unexpected split completion has been received.
1
An unexpected split completion has been received.
18
RW
Split Completion Discarded
This bit is set if the bridge discards a split completion moving toward the primary bus because the requester
would not accept it.
0
No split completion has been discarded.
1
A split completion has been discarded.
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