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| 型號(hào)： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 74/144頁(yè) |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_pcix_regs.fm.01
October 15, 2001
Configuration Registers
Page 35 of 144
5. Configuration Registers
This section describes the standard and device specific configuration registers contained within the bridge.
These registers provide various control and status reporting functions. Registers are accessible from the
primary interface using the configuration read and configuration write commands.
5.1 Configuration Space
The PCI/PCI-X specifications define a separate address space called the configuration space in which the
configuration registers are located. It is a contiguous block of 256 bytes, subdivided into two regions:
1. The first 64 bytes are the PCI configuration space header region, which provides for identification, con-
figuration, and recovery capabilities.
2. The remaining 192 bytes are the PCI device dependent region, which provides for device specific config-
uration data. Modification of the reserved bits contained within this region may have serious and unpre-
dictable effects on the operation of the IBM 133 PCI-X Bridge R2.0.
In addition, there are two versions of the PCI configuration space:
1. The standard configuration is often referred to as a “Type x‘00’ PCI configuration space header” because
the value x‘00’ is stored in the PCI header type register (at offset x‘0E’).
2. The PCI-to-PCI bridge configuration is often referred to as a “Type x‘01’ PCI configuration space header”
because the value x‘01’ is stored in the PCI header type register (at offset x‘0E’).
This chapter provides a specification for only the Type x‘01’ PCI configuration space header.
The mandatory PCI configuration space registers perform these operations:
Detect PCI devices and their functions
Initialize PCI devices
Assign system resources to PCI devices
Support catastrophic error recovery
5.2Typex‘01’ PCI Configuration Space Header
5.2.1 Description
The 64-byte PCI configuration space header region has two subregions:
The first 16 bytes are the PCI device independent region with registers for:
- Vendor ID
-Device ID
- Command
-Status
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