參數(shù)資料
型號(hào)： IBM21P100BGC
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA304
封裝： 31 X 31 MM, PLASTIC, BGA-304
文件頁數(shù)： 120/144頁
文件大小： 5197K
代理商： IBM21P100BGC
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_pcix_regs.fm.01
October 15, 2001
Configuration Registers
Page 77 of 144
5.2.5.10 Discard Timer Control Register
This register controls the duration and enabling of the discard timers.
There is a unique discard timer for every delayed transaction enqueued in the bridge. A discard timer begins
counting at the receipt of a delayed transaction in the conventional PCI mode. The timer is reset each time
the initiating bus master retries the transaction. The timer is stopped and reset when the transaction is
completed. If a discard timer expires, the associated transaction is discarded, data buffers and control
resources are freed, and the appropriate status bit is set in the retry and timer status register.
Address Offset
x‘68’
Access
Read/Write
Reset Value
x‘00’
Reserved
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7
6
5
4
3
2
1
0
Bit(s)
Access
FieldNameand Description
7:4
RO
Reserved
3
RW
Primary Discard Timer Short Duration
Controls the number of PCI clocks that the primary discard timer allows before it expires.
0
Use bit 8 of the bridge control register to indicate how many PCI clocks should be allowed before the
primary discard timer expires.
1Use 2
6 PCI clocks for the value of the primary discard timer.
2
RW
Secondary Discard Timer Short Duration
Controls the number of PCI clocks that the secondary discard timer allows before it expires.
0
Use bit 9 of the bridge control register to indicate how many PCI clocks should be allowed before the
secondary discard timer expires.
1Use 26 PCI clocks for the value of the secondary discard timer.
1
RW
Primary Discard Timer Disable
Controls the disabling of the primary discard timer in conjunction with bit 11 of the bridge control register.
0
Enable the primary discard timer.
1
Disable primary discard timer.
0
RW
Secondary Discard Timer Disable
Controls the disabling of the secondary discard timer in conjunction with bit 11 of the bridge control register.
0
Enable the secondary discard timer.
1
Disable secondary discard timer.
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