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參數(shù)資料
| 型號(hào)： | L64360 |
| 廠商： | LSI Corporation |
| 英文描述： | Highly Integrated ATM Segmentation and Reassembly (SAR) Engine optimized for internetworking applications(用于優(yōu)化網(wǎng)絡(luò)的高度集成的異步傳輸模式-分段和重組處理芯片) |
| 中文描述： | 高度集成的自動(dòng)柜員機(jī)分段和重組（SAR）的網(wǎng)絡(luò)應(yīng)用（用于優(yōu)化網(wǎng)絡(luò)的高度集成的異步傳輸模式-分段和重組處理芯片優(yōu)化引擎） |
| 文件頁(yè)數(shù)： | 99/232頁(yè) |
| 文件大?。?/td> | 1389K |
| 代理商： | L64360 |
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ATM Cell Size
9-3
9.2
ATM Cell Size
The user can program the size of an ATM cell (up to 64 bytes) to support
applications that employ extra header fields to convey switch specific
information. The typical ATM cell in the VCR is 52 bytes, but cells can be
56, 60, or 64 bytes. The HEC value is generated and inserted into the cell
as it is passed out of the ATMizer Architecture. Therefore, the actual ATM
cell on the line could be 53, 57, 61, or 65 bytes.
The APU firmware creates cells from memory-mapped CS-PDUs, Real-
time Data Streams, or from existing memory resident cells. The cells are
built in cell holding areas inside the VCR. Once built, the APU firmware
transfers the cells, one byte at a time, through the ACI to the TCS Framing
Circuitry. The ACI contains special buffering circuitry to decouple the
ATMizer Architecture System Clock frequency from the clock frequency
required by the Transmission Convergence Sublayer framing circuitry.
The ACI is driven by the ATM line-derived byte clocks.
In ATM, raw cell data is combined with certain overhead information to
form transmission frames. The logic that performs this framing is in the
Transmission Convergence Sublayer. ATM supports framing modes that
insert several framing bytes into each transmission frame. As a result,
bytesarereceivedthatdonotcorrespondtodatatransfersbetweentheTCS
Framing Logic and the ACI Ports. The system may need to gap data trans-
fers to and from the ACI Ports, so there must be a way to signal to the
ATMizer Architecture when no data transactions are desired (to create
gapsinthedatastream).IntheATMizerArchitectureapplication,external
logic can indicate that a data transfer is not desired by either stopping the
ACIPortclock(s)(runningtheACIPortsoffofgappedclocks)ordeassert-
ing TX_ACK or RC_ACK (running the ACIs off of the free running line
clocks and using a data acknowledge mechanism to deal with gapping).
9.3
Frequency
Decoupling
The ATMizer Architecture contains all of the logic necessary for decou-
pling the ATMizer Architecture’s internal clock (the System Clock) from
the clock rates of the transmission lines. The system designer clocks byte-
wide data out of the ATMizer Architecture that is used to drive the trans-
mission line and clocks data into the ATMizer Architecture derived from
the received data stream. All frequency decoupling and metastability
issues are dealt with inside the ACI circuitry. The ATMizer Architecture
uses a simple handshake acknowledgment mechanism to allow external
logic to pause data transfers between the ATMizer Architecture and the
line transceivers. The pause may be required if external logic suspends the
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| L64364 | Highly Integrated ATM Segmentation and Reassembly (SAR) Engine optimized for internetworking applications(用于優(yōu)化網(wǎng)絡(luò)的高度集成的異步傳輸模式-分段和重組處理芯片) |
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