參數(shù)資料
型號(hào)： UPD488448FB-C80-45-DQ1
廠商： NEC Corp.
英文描述： 128 M-bit Direct Rambus⑩ DRAM
中文描述： 128 M位DRAM的直接Rambus的⑩
文件頁數(shù)： 72/80頁
文件大?。?/td> 1902K
代理商： UPD488448FB-C80-45-DQ1
Data Sheet M14837EJ3V0DS00
72
μ
PD488448 for Rev. P
PREX
Precharge command in XOP field.
SETF
Set fast clock command from SOP field.
PSX
INIT register field – PDN/NAP exit.
SETR
Set reset command from SOP field.
PSR
INIT register field – PDN self-refresh.
SINT
PVER
CNFGB register field – protocol version.
Serial interval packet for control register
read/write transactions.
Q
Read data packet on DQ pins.
SIO0,SIO1
CMOS serial pins for control registers.
R
Row address field of ROWA packet.
SOP
Serial opcode field in SRQ.
RBIT
CNFGB register field - #row address bits.
SRD
Serial read opcode command from SOP.
RD/RDA
Read (/precharge) command in COP field.
SRP
INIT register field – Serial repeat bit.
read
Operation of accessing sense amp data.
SRQ
receive
Serial request packet for control register
read/write transactions.
Moving information from the Channel into the
RDRAM (a serial stream is demuxed).
STBY
Power state – ready for ROW packets.
REFA
Refresh-activate command in ROP field.
SVER
Control register – stepping version.
REFB
Control register – next bank (self-refresh).
SWR
Serial write opcode command from SOP.
REFBIT
TCAS
TCLSCAS register field – t
CAS
core delay.
CNFGA register field – ignore bank bits (for
REFA and self-refresh).
TCLS
TCLSCAS register field – t
CLS
core delay.
REFP
Refresh-precharge command in ROP field.
TCLSCAS
Control register – t
CAS
and t
CLS
delay.
REFR
Control register – next row for REFA.
TCYCLE
Control register – t
CYCLE
delay.
refresh
Periodic operations to restore storage cells.
TDAT
Control register – t
DAC
delay.
retire
TEST77
Control register – for test purposes.
The automatic operation that stores write
buffer into sense amp after WR command.
TEST78
Control register – for test purposes.
RLX
RLXC, RLXR, RLXX relax commands.
TRDLY
Control register – t
RDLY
delay.
RLXC
Relax command in COP field.
transaction
ROW, COL, DQ packets for memory access.
RLXR
Relax command in ROP field.
transmit
RLXX
Relax command in XOP field.
Moving information from the RDRAM onto
the Channel (parallel word is muxed).
ROP
Row-opcode field in ROWR packet.
WR/WRA
Write (/precharge) command in COP field.
row
2
CBIT
dualocts of cells (bank/sense amp).
write
Operation of modifying sense amp data.
ROW
Pins for row-access control
XOP
Extended opcode field in COLX packet.
ROW
ROWA or ROWR packets on ROW pins.
ROWA
Activate packet on ROW pins.
ROWR
Row operation packet on ROW pins.
RQ
Alternate name for ROW/COL pins.
RSL
Rambus Signal levels.
SAM
Sample (I
OL
) command in XOP field.
SA
Serial address packet for control register
transactions w/ SA address field.
SBC
Serial broadcast field in SRQ.
SCK
CMOS clock pin.
SD
Serial data packet for control register
transactions w/ SD data field.
SDEV
Serial device address in SRQ packet.
SDEVID
INIT register field – Serial device ID.
self-refresh
Refresh mode for PDN and NAP.
sense amp
Fast storage that holds copy of bank’s row.
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