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參數(shù)資料
| 型號： | UPD488448FB-C80-45-DQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁數(shù)： | 63/80頁 |
| 文件大小： | 1902K |
| 代理商： | UPD488448FB-C80-45-DQ1 |
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Data Sheet M14837EJ3V0DS00
63
μ
PD488448 for Rev. P
33. CMOS - Receive Timing
Figure 33-1 is a timing diagram which shows the detailed requirements for the CMOS input signals.
The CMD and SIO0 signals are inputs which receive information transmitted by a controller (or by another RDRAM’s
SIO1 output). SCK is the CMOS clock signal driven by the controller. All signals are high true.
The cycle time, high phase time, and low phase time of the SCK clock are t
CYCLE1
, t
CH1
and t
CL1
, all measured at the
50 % level. The rise and fall times of SCK, CMD, and SIO0 are t
DR1
and t
DF1
, measured at the 20 % and 80 % levels.
The CMD signal is sampled twice per t
CYCLE1
interval, on the rising edge (odd data) and the falling edge (even data).
The set/hold window of the sample points is t
S1
/t
H1
. The SCK and CMD timing points are measured at the 50 % level.
The SIO0 signal is sampled once per t
CYCLE1
interval on the falling edge. The set/hold window of the sample points
is t
S2
/t
H2
. The SCK and SIO0 timing points are measured at the 50 % level.
Figure 33-1 CMOS Timing - Data Signals for Receive
V
IH,CMOS
80%
50%
20%
V
IL,CMOS
SCK
even
odd
V
IH,CMOS
80%
20%
V
IL,CMOS
CMD
t
DR2
t
DF2
t
S1
50%
t
DR2
t
DF2
CYCLE1
t
CH1
t
CL1
t
t
H1
t
S1
t
H1
V
IH,CMOS
80%
20%
V
IL,CMOS
SIO0
t
DR1
t
DF1
t
S2
50%
t
H2
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