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參數(shù)資料
| 型號： | UPD488448FB-C80-45-DQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁數(shù)： | 44/80頁 |
| 文件大?。?/td> | 1902K |
| 代理商： | UPD488448FB-C80-45-DQ1 |
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Data Sheet M14837EJ3V0DS00
44
μ
PD488448 for Rev. P
Figure 22-1 Control Registers (4/7)
Control Register : NAPX
Address : 045
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
DQS
NAPX4..0
NAPXA4..0
Read/write register.
Reset value is undefined.
Note t
SCYCLE
is
t
CYCLE1
(SCK cycle time).
Field
Description
DQ Select. This field specifies the number of SCK cycles (0
≥
0.5 cycles, 1
≥
1.5 cycles) between the CMD pin
framing sequence and the device selection on DQ5..0. see Figure 23-4. This field must be written with a ”1” for this
RDRAM.
Nap Exit Phase A plus B. This field specifies the number of SCK cycles during the first plus second phases for exiting
NAP mode. It must satisfy:
NAPX
t
SCYCLE
≥
NAPXA
t
SCYCLE
+t
NAPXB
,
MAX
Do not set this field to zero.
Nap Exit Phase A. This field specifies the number of SCK cycles during the first phase for exiting NAP mode. It must
satisfy:
NAPXA
t
SCYCLE
≥
t
NAPXA
,
MAX
Do not set this field to zero.
DQS
NAPX4..0
NAPXA4..0
Control Register : PDNXA
Address : 046
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
PDNXA4..0
Read/write register.
Reset value is undefined.
Field
Description
PDN Exit Phase A. This field specifies the number of (64
SCK cycle) units during the first phase for exiting PDN
mode. It must satisfy:
PDNXA
64
t
SCYCLE
≥
t
PDNXA
,
MAX
Do not set this field to zero.
Note – only PDNXA4..0 are implemented.
Note – t
SCYCLE
is t
CYCLE1
(SCK cycle time).
PDNXA4..0
Control Register : PDNX
Address : 047
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDNX2..0
Read/write register.
Reset value is undefined.
Field
Description
PDN Exit Phase A puls B. This field specifies the number of (256
SCK cycle) units during the first plus second phases
for exiting PDN mode. It must satisfy:
PDNX
256
t
SCYCLE
≥
PDNXA
64
t
SCYCLE
+t
PDNXB
,
MAX
It this equation can’t be satisfied, then the maximum PDNX value should be written, and the t
S4
/ t
H4
timing window will
be modified (see Figure 23-4).
Do not set this field to zero.
Note – only PDNX2..0 are implemented.
Note – t
SCYCLE
is t
CYCLE1
(SCK cycle time).
PDNX2..0
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