參數(shù)資料
型號(hào)： UPD488448FB-C80-45-DQ1
廠商： NEC Corp.
英文描述： 128 M-bit Direct Rambus⑩ DRAM
中文描述： 128 M位DRAM的直接Rambus的⑩
文件頁(yè)數(shù)： 20/80頁(yè)
文件大?。?/td> 1902K
代理商： UPD488448FB-C80-45-DQ1
Data Sheet M14837EJ3V0DS00
20
μ
PD488448 for Rev. P
8. COL-to-COL Packet Interaction
Figure 8-1 shows three arbitrary packets on the
COL pins. Packets “b” and “c” must be separated by
an interval t
CCDELAY
which depends upon the
command and address values in all three packets.
Table 8-1 summarizes the t
CCDELAY
values for all
possible cases.
Cases CC1 through CC5 summarize the rules for
every situation other than the case when COPb is a
WR command and COPc is a RD command. In
CC3, when a RD command is followed by a WR
command, a gap of t
CAC
-
t
CWD
must be inserted
between the two COL packets. See Figure 4-1 for
more explanation of why this gap is needed. For
cases CC1, CC2, CC4, and CC5, there is no
restriction (t
CCDELAY
is t
CC
).
In cases CC6 through CC10, COPb is a WR command and COPc is a RD command. The t
CCDELAY
value needed
between these two packets depends upon the command and address in the packet with COPa. In particular, in case
CC6 when there is WR-WR-RD command sequence directed to the same device, a gap will be needed between the
packets with COPb and COPc. The gap will need a COLC packet with a NOCOP command directed to any device in
order to force an automatic retire to take place. Figure 15-2 (right) provides a more detailed explanation of this case.
In case CC10, there is a RD-WR-RD sequence directed to the same device. If a prior write to the same device is
unretired when COPa is issued, then a gap will be needed between the packets with COPb and COPc as in case
CC6. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an
automatic retire to take place.
Cases CC7, CC8, and CC9 have no restriction (t
CCDELAY
is t
CC
).
For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC
packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation
PREC to take place. This precharge may be converted to an equivalent PRER command on the ROW pins using the
rules summarized in Figure 12-2.
Table 8-1 COL-to-COL Packet Interaction - Rules
Case #
COPa
Da
Ba
Ca1 COPb
Db
Bb
Cb1 COPc
Dc
Bc
Cc1
t
CCDELAY
Example
CC1
CC2
CC3
CC4
CC5
xxxx
xxxx
xxxx
xxxx
xxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
NOCOP Db
RD, WR Db
RD
RD
WR
Bb
Bb
Bb
Bb
Bb
Cb1 xxxx
Cb1 NOCOP xxxxx
Cb1 WR
Cb1 RD
Cb1 WR
xxxxx
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
t
CC
t
CC
t
CC
+
t
CAC
-
t
CWD
t
CC
t
CC
Db
Db
Db
xxxxx
xxxxx
xxxxx
Figure 4-1
Figure 13-1
Figure 14-1
CC6
CC7
CC8
CC9
CC10
WR
WR
WR
NOCOP == Db
RD
== Db
== Db
/= Db
x
x
x
x
x
x..x
x..x
x..x
x..x
x..x
WR
WR
WR
WR
WR
Db
Db
Db
Db
Db
Bb
Bb
Bb
Bb
Bb
Cb1 RD
Cb1 RD
Cb1 RD
Cb1 RD
Cb1 RD
== Db
/= Db
== Db
== Db
== Db
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
t
RTR
t
CC
t
CC
t
CC
t
CC
Figure 15-1
== Db
Figure 8-1 COL-to-COL Packet Interaction- Timing
CTM/CFM
DQA7..0
DQB7..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
T
17
T
18
T
19
COPa a1
Transaction a: COPa
Transaction b: COPb
Transaction c: COPc
COPc c1
a1 = {Da,Ba,Ca1}
b1 = {Db,Bb,Cb1}
c1 = {Dc,Bc,Cc1}
t
CCDELAY
COPb b1
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