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參數(shù)資料
| 型號(hào)： | UPD488448FB-C80-45-DQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁(yè)數(shù)： | 69/80頁(yè) |
| 文件大?。?/td> | 1902K |
| 代理商： | UPD488448FB-C80-45-DQ1 |
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Data Sheet M14837EJ3V0DS00
69
μ
PD488448 for Rev. P
39. Capacitance and Inductance
Figure 39-1 shows the equivalent load circuit of the RSL and CMOS pins. The circuit models the load that the device
presents to the Channel.
This circuit does not include pin coupling effects that are often present in the packaged device. Because coupling
effects make the effective single-pin inductance L
I
, and capacitance C
I
, a function of neighboring pins, these
parameters are intrinsically data-dependent. For purposes of specifying the device electrical loading on the Channel,
the effective L
I
and C
I
are defined as the worst-case values over all specified operating conditions.
L
I
is defined as the effective pin inductance based on the device pin assignment. Because the pad assignment
places each RSL signal adjacent to an AC ground (a GND or V
DD
pin), the effective inductance must be defined
based on this configuration. Therefore, L
I
assumes a loop with the RSL pin adjacent to an AC ground.
C
I
is defined as the effective pin capacitance based on the device pin assignment. It is the sum of the effective
package pin capacitance and the IO pad capacitance.
Figure 39-1 Equivalent Load Circuit for RSL Pins
L
C
R
I
I
I
Pad
L
C
R
I
I
I
Pad
CTM,CTMN,
CFM,CFMN Pin
L
C
I,CMOS
I
Pad
L
C
I,CMOS
I,CMOS,SIO
Pad
DQA,DQB,RQ Pin
GND Pin
GND Pin
SCK,CMD Pin
GND Pin
SIO0,SIO1 Pin
GND Pin
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