- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379500 > UPD488448FB-C80-45-DQ1 (NEC Corp.) 128 M-bit Direct Rambus⑩ DRAM PDF資料下載
參數(shù)資料
| 型號： | UPD488448FB-C80-45-DQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁數(shù)： | 50/80頁 |
| 文件大?。?/td> | 1902K |
| 代理商： | UPD488448FB-C80-45-DQ1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
Data Sheet M14837EJ3V0DS00
50
μ
PD488448 for Rev. P
Once the RDRAM is in ATTN, ATTNW, or ATTNR states, it will remain there until it is explicitly returned to the STBY
state with a RLX command. A RLX command may be given in an ROWR, COLC, or COLX packet (see the left side
of Figure 23-2). It is usually given after all banks of the RDRAM have been precharged; if other banks are still
activated, then the RLX command would probably not be given.
If a broadcast ROWA packet or ROWR packet (with the ATTN command) is received, the RDRAM’s power state
doesn’t change. If a broadcast ROWR packet with RLXR command is received, the RDRAM goes to STBY.
Figure 23-2 STBY Entry (left) and STBY Exit (right)
STBY
ATTN
CTM/CFM
DQA7..0
DQB7..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
17
T
21
T
18
T
22
T
19
23
T
0
CTM/CFM
DQA7..0
DQB7..0
COL4
..COL0
ROW2
..ROW0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
t
AS
RLXR
Power
State
ATTN
Power
State
STBY
t
SA
ROP a0
RLXC
RLXX
TFRMt
CYCLE
COCCCCOP a0
XOP a1
XOP a0
ROP=non-broadcast
R
OWA or ROWR/ATTN
a0={d0, b0, r0}
a
1={d1, b1, c1}
No COL packets may
b
e
placed in the thre
e
indicated positions; i.e.
a
t
(TFRM-{1,2,3})
t
CYCLE
.
A COL packet to device d0
(
or any other device) is okay
at
(TFRM)t
CYCLE
or later.
A COL packet to another device
(d1!=d0
) is okay
at
(TFRM-4)t
CYCLE
or earlier.
Figure 23-3 shows the NAP entry sequence (left). NAP state is entered by sending a NAPR command in a ROW
packet. A time t
ASN
is required to enter NAP state (this specification is provided for power calculation purposes). The
clock on CTM/CFM must remain stable for a time t
CD
after the NAPR command.
Figure 23-3 NAP Entry (left) and PDN Entry (right)
CTM/CFM
DQA7..0
DQB7..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
17
T
21
T
18
T
22
T
19
23
T
0
CTM/CFM
DQA7..0
DQB7..0
COL4
..COL0
ROW2
..ROW0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
t
ASN
ROP a0
(NAPR)
Power
State
ATTN/STBY
Note
Power
State
NAP
ATTN/STBY
Note
PDN
t
ASP
ROP a0
(PDNR)
Note
The(eventual) NAP/PDN exit will be to the same ATTN/STBY state the RDRAM was in prior to NAP/PDN entry
t
CD
t
CD
a0={d0, b0, r0, c0}
a
1={d1, b1, c1, c1}
No ROW or COL packets directed
to device d0 may overlap the
restricted interval. No broadcast
ROW packets may overlap
the quiet interval.
ROW or COL packets to a device
other than d0 may overlap the
restricted interval.
restricted
ROP a1
COP a0
XOP a0
COP a1
XOP a1
restricted
restricted
ROP a1
COP a0
XOP a0
COP a1
XOP a1
restricted
ROW or COL packets directed
to device d0 after the restricted
interval will be ignored.
t
NPQ
t
NPQ
The RDRAM may be in ATTN or STBY state when the NAPR command is issued. When NAP state is exited, the
RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state and a RLXR command is
specified with NAPR, then the RDRAM will return to STBY state when NAP is exited.
Figure 23-3 also shows the PDN entry sequence (right). PDN state is entered by sending a PDNR command in a
ROW packet. A time t
ASP
is required to enter PDN state (this specification is provided for power calculation
purposes). The clock on CTM/CFM must remain stable for a time t
CD
after the PDNR command.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD488448FB-C80-45-DQ2 | 128 M-bit Direct Rambus⑩ DRAM |
| UPD488448FB-C71-45-DQ1 | 128 M-bit Direct Rambus⑩ DRAM |
| UPD488448FB-C71-45-DQ2 | 128 M-bit Direct Rambus⑩ DRAM |
| UPD488448FB-C60-53-DQ2 | 128 M-bit Direct Rambus⑩ DRAM |
| UPD488448FF-C80-45-DQ1 | 128 M-bit Direct Rambus⑩ DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD4990AG-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD4991ACX-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD4992CX-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD50256CP15 | 制造商:HIT 功能描述:50256 HITACHI'86 SMT N9F8A |
| UPD50256CP-15 | 制造商:HIT 功能描述:50256 HITACHI'86 SMT N9F8A |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。