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參數(shù)資料
| 型號(hào)： | UPD488448FB-C80-45-DQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁(yè)數(shù)： | 48/80頁(yè) |
| 文件大?。?/td> | 1902K |
| 代理商： | UPD488448FB-C80-45-DQ1 |
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Data Sheet M14837EJ3V0DS00
48
μ
PD488448 for Rev. P
23. Power State Management
Table 23-1 summarizes the power states available to a Direct RDRAM. In general, the lowest power states have
the longest operational latencies. For example, the relative power levels of PDN state and STBY state have a ratio of
about 1:110, and the relative access latencies to get read data have a ratio of about 250:1.
PDN state is the lowest power state available. The information in the RDRAM core is usually maintained with self-
refresh; an internal timer automatically refreshes all rows of all banks. PDN has a relatively long exit latency because
the TCLK/RCLK block must resynchronize itself to the external clock signal.
NAP state is another low-power state in which either self-refresh or REFA-refresh are used to maintain the core.
See
24. Refresh
for a description of the two refresh mechanisms. NAP has a shorter exit latency than PDN because
the TCLK/RCLK block maintains its synchronization state relative to the external clock signal at the time of NAP
entry. This imposes a limit (t
NLIMIT
) on how long an RDRAM may remain in NAP state before briefly returning to STBY
or ATTN to update this synchronization state.
Table 23-1 Power State Summary
Power State Description
Blocks consuming power Power state
Description
Blocks consuming power
PDN
Powerdown state.
Self-refresh
NAP
Nap state. Similar to
PDN except lower
wake-up latency.
Attention state.
Ready for ROW and
COL packets.
Self-refresh or
REFA-refresh
TCLK/RCLK-Nap
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
DQ demux receiver
Core power
STBY
Standby state.
Ready for ROW
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
ATTN
ATTNR
Attention read state.
Ready for ROW and
COL packets.
Sending Q (read data)
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
DQ mux transmitter
Core power
ATTNW
Attention write state.
Ready for ROW and
COL packets.
Ready for D (write data)
packets.
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