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參數(shù)資料
| 型號： | UPD488448FB-C80-45-DQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁數(shù)： | 35/80頁 |
| 文件大?。?/td> | 1902K |
| 代理商： | UPD488448FB-C80-45-DQ1 |
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Data Sheet M14837EJ3V0DS00
35
μ
PD488448 for Rev. P
21. Initialization
Figure 21-1 SIO Pin Reset Sequence
SCK
CMD
SIO0
T
16
0000000000000000
00000000...00000000
0000000000000000
SIO1
T
0
The packet is repeated
from SIO0 to SIO1
1
1
1
1
0
0
0
0
00001100
Initialization refers to the process that a controller must go through after power is applied to the system or the system
is reset. The controller prepares the RDRAM sub-system for normal Channel operation by (primarily) using a
sequence of control register transactions on the serial CMOS pins. The following steps outline the sequence seen by
the various memory subsystem components (including the RDRAM components) during initialization. This sequence
is available in the form of reference code. Contact Rambus Inc. for more information.
1.0 Start Clocks
This step calculates the proper clock frequencies for PClk (controller logic), SynClk (RAC block), RefClk (DRCG
component), CTM (RDRAM component), and SCK (SIO block).
2.0 RAC Initialization
This step causes the INIT block to generate a sequence of pulses which resets the RAC, performs RAC
maintainance operations, and measures timing intervals in order to ensure clock stability.
3.0 RDRAM Initialization
This stage performs most of the steps needed to initialize the RDRAMs. The rest are performed in stages 5.0,
6.0, and 7.0. All of the steps in 3.0 are carried out through the SIO block interface.
3.1/3.2 SIO Reset
This reset operation is performed before any SIO control register read or write transactions. It clears six
registers (TEST34, CCA, CCB, SKIP, TEST78, and TEST79) and places the INIT register into a special state
(all bits cleared except SKP and SDEVID fields are set to ones).
3.3 Write TEST77 Register
The TEST77 register must be explicitly written with zeros before any other registers are read or written.
3.4 Write TCYCLE Register
The TCYCLE register is written with the cycle time t
CYCLE
of the CTM clock (for Channel and RDRAMs) in
units of 64ps. The t
CYCLE
value is determined in stage 1.0.
3.5 Write SDEVID Register
The SDEVID (serial device identification) register of each RDRAM is written with a unique address value so
that directed SIO read and write transactions can be performed. This address value increases from 0 to 31
according to the distance an RDRAM is from the ASIC component on the SIO bus (the closest RDRAM is
address 0).
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