參數(shù)資料
型號(hào)： UPD488448FB-C80-45-DQ1
廠商： NEC Corp.
英文描述： 128 M-bit Direct Rambus⑩ DRAM
中文描述： 128 M位DRAM的直接Rambus的⑩
文件頁(yè)數(shù)： 62/80頁(yè)
文件大?。?/td> 1902K
代理商： UPD488448FB-C80-45-DQ1
Data Sheet M14837EJ3V0DS00
62
μ
PD488448 for Rev. P
32. RSL - Transmit Timing
Figure 32-1 is a timing diagram which shows the detailed requirements for the RSL output signals on the Channel.
The DQA and DQB signals are outputs to transmit information that is received by a Direct RAC on the Channel.
Each signal is driven twice per t
CYCLE
interval. The beginning and end of the even transmit window is at the 75 %
point of the previous cycle and at the 25 % point of the current cycle. The beginning and end of the odd transmit
window is at the 25 % point and at the 75 % point of the current cycle. These transmit points are measured relative to
the crossing points of the falling CTM clock edge. The size of the actual transmit window is less than the ideal
t
CYCLE
/2, as indicated by the non-zero valued of t
Q,MIN
and t
Q,MAX
. The t
Q
parameters are measured at the 50 % voltage
point of the output transition.
The t
QR
and t
QF
rise- and fall-time parameters are measured at the 20 % and 80 % points of the output transition.
Figure 32-1 RSL Timing - Data Signals for Transmit
V
CIH
80%
50%
20%
V
CIL
CTM
CTMN
even
t
Q,MIN
odd
CYCLE
V
QH
80%
20%
V
QL
DQA
DQB
t
QR
t
QF
t
Q,MAX
t
Q,MIN
t
Q,MAX
0.25t
50%
CYCLE
0.75t
CYCLE
0.75t
V
X-
V
X+
V
CM
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