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參數(shù)資料
| 型號： | UPD488448FB-C80-45-DQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁數(shù)： | 66/80頁 |
| 文件大?。?/td> | 1902K |
| 代理商： | UPD488448FB-C80-45-DQ1 |
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Data Sheet M14837EJ3V0DS00
66
μ
PD488448 for Rev. P
35. RSL - Domain Crossing Window
When read data is returned by the RDRAM, information must cross from the receive clock domain (CFM) to the
transmit clock domain (CTM). The t
TR
parameter permits the CFM to CTM phase to vary though an entire cycle ; i.e.
there is no restriction on the alignment of these two clocks. A second parameter t
DCW
is needed in order to describe
how the delay between a RD command packet and read data packet varies as a function of the t
TR
value.
Figure 35-1 shows this timing for five distinct values of t
TR
. Case A (t
TR
=0) is what has been used throughout this
document. The delay between the RD command and read data is t
CAC
. As t
TR
varies from zero to t
CYCLE
(cases A
through E), the command to data delay is (t
CAC
-t
TR
). When the t
TR
value is in the range 0 to t
DCW,MAX
, the command to
data delay can also be (t
CAC
-t
TR
-t
CYCLE
). This is shown as cases A’ and B’ (the gray packets). Similarly, when the t
TR
value is in the range (t
CYCLE
+t
DCW,MIN
) to t
CYCLE
, the command to data delay can also be (t
CAC
-t
TR
+t
CYCLE
). This is shown
as cases D’ and E’ (the gray packets). The RDRAM will work reliably with either the white or gray packet timing. The
delay value is selected at initialization, and remains fixed thereafter.
Figure 35-1 RSL Timing - Crossing Read Domains
CFM
RDa1
CYCLE
t
Q(a1)
Q(a1)
TR
t
TR
t
Q(a1)
Q(a1)
TR
t
Q(a1)
Q(a1)
Q(a1)
Q(a1)
Q(a1)
CAC TR
t
CAC TR CYCLE
t
TR
t
TR
t
COL
CTM
DQA/B
DQA/B
CTM
DQA/B
DQA/B
CTM
DQA/B
CTM
DQA/B
DQA/B
CTM
DQA/B
DQA/B
Case A t
=0
TR
Case A' t =0
Case B t =t
DCW,MAX
Case B' t =t
DCW,MAX
Case C t =0.5
t
CYCLE
Case D
t =t + t
Case D'
t =t + t
DCW,MIN
DCW,MIN
Case E t =t
CYCLE
TR
Case E' t =t
CYCLE
CAC TR
t
CAC TR CYCLE
t
CAC TR
t
CAC TR CYCLE
t
CAC TR
t
CAC TR
t
CAC
CYCLE
-t +t
t
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