參數(shù)資料
型號(hào)： UPD488448FB-C80-45-DQ1
廠商： NEC Corp.
英文描述： 128 M-bit Direct Rambus⑩ DRAM
中文描述： 128 M位DRAM的直接Rambus的⑩
文件頁數(shù)： 30/80頁
文件大小： 1902K
代理商： UPD488448FB-C80-45-DQ1
Data Sheet M14837EJ3V0DS00
30
μ
PD488448 for Rev. P
16. Interleaved Write - Example
Figure 16-1 shows an example of an interleaved write transaction. Transactions similar to the one presented in
Figure 14-1 are directed to non-adjacent banks of a single RDRAM. This allows a new transaction to be issued once
every t
RR
interval rather than once every t
RC
interval (four times more often). The DQ data pin efficiency is 100% with
this sequence.
With two dualocts of data written per transaction, the COL, DQA, and DQB pins are fully utilized. Banks are
precharged using the WRA autoprecharge option rather than the PRER command in an ROWR packet on the ROW
pins.
In this example, the first transaction is directed to device Da and bank Ba. The next three transactions are directed
to the same device Da, but need to use different, non-adjacent banks Bb, Bc, Bd so there is no bank conflict. The
fifth transaction could be redirected back to bank Ba without interference, since the first transaction would have
completed by then (t
RC
has elapsed). Each transaction may use any value of row address (Ra, Rb, ...) and column
address (Ca1, Ca2, Cb1, Cb2, ...).
Figure 16-1 Interleaved Write Transaction with Two Dualoct Data Length
CTM/CFM
DQA7..0
DQB7..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
ACT a0
MSK (b2)
WRA c2
MSK (b1)
WR c1
WR b1
MSK (a1)
WRA b2
MSK (a2)
D (b2)
D (b1)
ACT b0
ACT c0
ACT d0
ACT e0
D (a2)
D (a1)
WR d1
MSK (c1)
D(c1)
ACT f0
WR d2
MSK (c2)
WR e1
MSK (d1)
D (c2)
D (d1)
WR e2
MSK (d2)
D (z2)
D (z1)
D (x2)
D (y1)
D (y2)
MSK (z2)
t
CWD
WRA a2
MSK (z1)
WR a1
WR z1
MSK (y1)
WRA z2
MSK (y2)
Q (
t
RCD
t
RC
Transaction e can use the
same bank as transaction a
t
RR
f3 = {Da,Ba+2}
Transaction f: WR
f0 = {Da,Ba+2,Rf}
f1 = {Da,Ba+2,Cf1}
f2= {Da,Ba+2,Cf2}
e3 = {Da,Ba}
Transaction e: WR
e0 = {Da,Ba,Re}
e1 = {Da,Ba,Ce1}
e2= {Da,Ba,Ce2}
d3 = {Da,Ba+6}
Transaction d: WR
d0 = {Da,Ba+6,Rd}
d1 = {Da,Ba+6,Cd1}
d2= {Da,Ba+6,Cd2}
c3 = {Da,Ba+4}
Transaction c: WR
c0 = {Da,Ba+4,Rc}
c1 = {Da,Ba+4,Cc1}
c2= {Da,Ba+4,Cc2}
b3 = {Da,Ba+2}
Transaction b: WR
b0 = {Da,Ba+2,Rb}
b1 = {Da,Ba+2,Cb1}
b2= {Da,Ba+2,Cb2}
a3 = {Da,Ba}
Transaction a: WR
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
a2= {Da,Ba,Ca2}
z3 = {Da,Ba+6}
Transaction z: WR
z0 = {Da,Ba+6,Rz}
z1 = {Da,Ba+6,Cz1}
z2= {Da,Ba+6,Cz2}
y3 = {Da,Ba+4}
Transaction y: WR
y0 = {Da,Ba+4,Ry}
y1 = {Da,Ba+4,Cy1}
y2= {Da,Ba+4,Cy2}
相關(guān)PDF資料
PDF描述
UPD488448FB-C80-45-DQ2 128 M-bit Direct Rambus⑩ DRAM
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