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參數(shù)資料
| 型號： | UPD488448FB-C80-45-DQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁數(shù)： | 71/80頁 |
| 文件大?。?/td> | 1902K |
| 代理商： | UPD488448FB-C80-45-DQ1 |
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Data Sheet M14837EJ3V0DS00
71
μ
PD488448 for Rev. P
40. Glossary of Terms
ACT
Activate command from AV field.
D
Write data packet on DQ pins.
activate
To access a roe and place in sense amp.
DBL
CNFGB register field – doubled-bank.
activate
To access a row and place in sense amp.
DC
Device address field in COLC packet.
adjacent
device
An RDRAM on a Channel.
Two RDRAM banks which share sense amps
(also called doubled banks).
DEVID
ASYM
CCA register field for RSL V
OL
/ V
OH
.
Control register with device address that is
matched against DR, DC, and DX fields.
ATTN
Power state – ready for ROW / COL packets.
DM
Device match for ROW packet decode.
ATTNR
Power state – transmitting Q packets.
Doubled-bank
RDRAM with shared sense amp.
ATTNW
Power state – receiving D packets.
DQ
DQA and DQB pins.
AV
Opcode field in ROW packets.
DQA
Pins for data byte A.
bank
DQB
Pins for data byte B.
A block of 2
of the RDRAM.
RBIT
2
CBIT
storage cells in the core
DQS
NAPX register field – PDN/NAP exit.
BC
Bank address field in CLC packet.
DR,DR4T,DR4F
BBIT
CNFGA register field - # bank address bits.
Device address field and packet framing fields
in ROW and ROWE packets.
broadcast
An operation executed by all RDRAMs.
dualoct
16 bytes – the smallest addressable datum.
BR
Bank address field in ROW packets.
DX
Device address field in COLX packet.
bubble
field
A collection of bits in a packet.
Idle cycle(s) on RDRAM pins needed
because of a resource constraint.
INIT
Control register with initialization fields.
BYT
CNFGB register field – 9 bits per byte.
initialization
BX
Bank address field in COLX packet.
Configuring a Channel of RDRAMs so they
are ready to respond to transactions.
C
Column address field in COLC packet.
LSR
CNFGA register field – low-power self-refresh.
CAL
Calibrate (I
OL
) command in XOP field.
M
Mask opcode field (COLM/COLX packet).
CBIT
CNFGB register field - # column address bits.
MA
Field in COLM packet for masking byte A.
CCA
Control register – current control A.
MB
Field in COLM packet for masking byte B.
CCB
Control register – current control B.
MSK
Mask command in M field.
CFM,CFMN
Clock pins for receiving packets.
MVER
Control register – manufacturer ID.
Channel
ROW / COL / DQ pins and external wires.
NAP
Power state – needs SCK/CMD wakeup.
CLRR
Clear reset command from SOP field.
NAPR
Nap command in ROP field.
CMD
CMOS pins for initialization / power control.
NAPRC
Conditional nap command in ROP field.
CNFGA
Control register with configuration fields.
NAPXA
NAPX register field – NAP exit delay A.
CNFGB
Control register with configuration fields.
NAPXB
NAPX register field – NAP exit delay B.
COL
Pins for column-access control.
NOCOP
No-operation command in COP field.
COLC
Column operation packet on COL pins.
NOROP
No-operation command in ROP field.
COLM
Write mask packet on COL pins.
NOXOP
No-operation command in XOP field.
column
NSR
INIT register field – NAP self-refresh.
Rows in a bank or activated in sense amps
have 2
CBTI
dualocts column storage.
packet
A collection of bits carried on the Channel.
Command
A decoded bit-combination from a field.
PDN
Power state – needs SCK/CMD wakeup.
COLX
Extended operation packet on COL pins.
PDNR
Powerdown command in ROP field.
controller
PDNXA
Control register – PDN exit delay A.
A logic-device which drives the ROW / COL
/ DQ wires for a Channel of RDRAMs.
PDNXB
Control register – PDN exit delay B.
COP
Column opcode field in COLC packet.
pin efficiency
The fraction of non-idle cycles on a pin.
core
The banks and sense amps of an RDRAM.
PRE
PREC, PRER, PREX precharge commands.
CTM, CTMN
Clock pins for transmitting packets.
PREC
Precharge command in COP field.
Current control
precharge
Prepares sense amp and bank for activate.
Periodic operations to update the proper I
OL
Value of RSL output drivers.
PRER
Precharge command in ROP field.
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