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參數(shù)資料
| 型號： | UPD488448FB-C80-45-DQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁數(shù)： | 14/80頁 |
| 文件大?。?/td> | 1902K |
| 代理商： | UPD488448FB-C80-45-DQ1 |
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Data Sheet M14837EJ3V0DS00
14
μ
PD488448 for Rev. P
Table 3-3 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC
packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations
(moving data from the write buffer to a sense amp) happen automatically. See Figure 15-1 for a more detailed
description.
The COLC packet can also specify a PREC command, which precharges a bank and its associated sense amps.
The RDA/WRA commands are equivalent to a combining RD/WR with a PREC. RLXC (relax) performs a power mode
transition. See
23. Power State Management
.
Table 3-3 COLC Packet Field Encodings
S
DC4..DC0
(select device)
Note1
COP3..0
Name
Command Description
0
1
1
1
- - - -
/= (DEVID4..0)
== (DEVID4..0)
== (DEVID4..0)
- - - - -
- - - - -
x000
x001
—
—
NOCOP
WR
No operation.
Retire write buffer of this device.
Retire write buffer of this device.
Retire write buffer of this device, then write column C5..C0 of bank
BC4..BC0 to write buffer.
Reserved, no operation.
Read column C5..C0 of bank BC4..BC0 of this device.
Retire write buffer of this device, then precharge bank BC4..BC0 (see
Figure 12-2).
Same as WR, but precharge bank BC4..BC0 after write buffer (with new
data) is retired.
Reserved, no operation.
Same as RD, but precharge bank BC4..BC0 afterward.
Move this device into the standby (STBY) power state (see Figure 23-2).
Note2
1
1
1
== (DEVID4..0)
== (DEVID4..0)
== (DEVID4..0)
x010
x011
x100
RSRV
RD
PREC
1
== (DEVID4..0)
x101
WRA
1
1
1
== (DEVID4..0)
== (DEVID4..0)
== (DEVID4..0)
x110
x111
1xxx
RSRV
RDA
RLXC
Notes 1.
“/=” means not equal, “==” means equal.
2.
An “x” entry indicates which commands may be combined. For instance, the two commands WR/RLXC
may be specified in one COP value(1001).
Table 3-4 shows the COLM and COLX field encodings. The M bit is asserted to specify a COLM packet with two 8
bit bytemask fields MA and MB. If the M bit is not asserted, an COLX is specified. It has device and bank address
fields, and an opcode field. The primary use of the COLX packet is to permit an independent PREX (precharge)
command to be specified without consuming control bandwidth on the ROW pins. It is also used for the CAL
(calibrate) and SAM (sample) current control commands (see
25. Current and Temperature Control
), and for the
RLXX power mode command (see
23. Power State Management
).
Table 3-4 COLM Packet and COLX Packet Field Encodings
M
DX4..DX0
(select device)
XOP4..0
Name
Command Description
1
0
0
0
0
0
0
0
- - - -
/= (DEVID4..0)
== (DEVID4..0) 00000
== (DEVID4..0) 1xxx0
== (DEVID4..0) x10x0
== (DEVID4..0) x11x0
== (DEVID4..0) xxx10
== (DEVID4..0) xxxx1
-
-
MSK
—
NOXOP
PREX
CAL
CAL / SAM
RLXX
RSRV
MB/MA bytemasks used by WR/WRA.
No operation.
No operation.
Precharge bank BX4..BX0 of this device (see Figure 12-2).
Calibrate (drive) I
OL
current for this device (see Figure 25-1).
Calibrate (drive) and Sample (update) I
OL
current for this device (see Figure 25-1).
Move this device into the standby (STBY) power state (see Figure 23-2).
Reserved, no operation.
Note
Note
An “x” entry indicates which commands may be combined. For instance, the two commands PREX/RLXX
may be specified in one XOP value (10010).
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