參數(shù)資料
型號(hào)： UPD488448FB-C80-45-DQ1
廠商： NEC Corp.
英文描述： 128 M-bit Direct Rambus⑩ DRAM
中文描述： 128 M位DRAM的直接Rambus的⑩
文件頁(yè)數(shù)： 67/80頁(yè)
文件大?。?/td> 1902K
代理商： UPD488448FB-C80-45-DQ1
Data Sheet M14837EJ3V0DS00
67
μ
PD488448 for Rev. P
36. Timing Parameters
Timing Parameters Summary
Para-
Description
MIN.
MAX.
Units
Figures
meter
-C80
-C71
-C60
-45
-45
-53
t
RC
Row Cycle time of RDRAM banks - the interval between ROWA packets
with ACT commands to the same bank.
28
28
28
—
t
CYCLE
Figure13-1
Figure14-1
Figure13-1
Figure14-1
t
RAS
RAS-asserted time of RDRAM bank - the interval between ROWA packet
with ACT command and next ROWR packet with PRER
same bank.
Row Precharge time of RDRAM banks - the interval between ROWR packet
with PRER
same bank.
Precharge-to-precharge time of RDRAM device - the interval between
successive ROWR packets with PRER
the same device.
RAS-to-RAS time of RDRAM device - the interval between successive
ROWA packets with ACT commands to any banks of the same device.
Note 1
command to the
20
20
20
Note 2
64
μ
s
t
CYCLE
t
RP
Note 1
command and next ROWA packet with ACT command to the
8
8
8
—
t
CYCLE
Figure13-1
Figure14-1
t
PP
Note 1
commands to any banks of
8
8
8
—
t
CYCLE
Figure10-3
t
RR
8
8
8
—
t
CYCLE
Figure12-1
t
RCD
RAS-to-CAS Delay - the interval from ROWA packet with ACT
command to COLC packet with RD or WR command. Note - the RAS-
to-CAS delay seen by the RDRAM core (t
RCD-C
) is equal to t
RCD-C
=
1
+
t
RCD
because of differences in the row and column paths through the
RDRAM interface.
9
7
7
—
t
CYCLE
Figure13-1
Figure14-1
t
CAC
CAS Access delay - the interval from RD command to Q read data. The
equation for t
CAC
is given in the TPARM register in Figure 22-1(5/7).
CAS Write Delay - interval from WR command to D write data.
CAS-to-CAS time of RDRAM bank - the interval between successive
COLC commands.
8
8
8
12
t
CYCLE
Figure4-1
t
CWD
t
CC
6
4
6
4
6
4
6
—
t
CYCLE
t
CYCLE
Figure4-1
Figure13-1
Figure14-1
Figure2-1
Figure15-1
t
PACKET
Length of ROWA, ROWR, COLC, COLM or COLX packet.
t
RTR
Interval from COLC packet with WR command to COLC packet which
causes retire, and to COLM packet with bytemask.
4
8
4
8
4
8
4
—
t
CYCLE
t
CYCLE
t
OFFP
The interval (offset) from COLC packet with RDA command, or from
COLC packet with retire command (after WRA automatic precharge), or
from COLC packet with PREC command, or from COLX packet with
PREX command to the equivalent ROWR packet with PRER. The
equation for t
OFFP
is given in the TPARM register in Figure 22-1(5/7).
Interval from last COLC packet with RD command to ROWR packet
with PRER.
Interval from last COLC packet with automatic retire command to
ROWR packet with PRER.
4
4
4
4
t
CYCLE
Figure14-2
t
RDP
4
4
4
—
t
CYCLE
Figure13-1
t
RTP
4
4
4
—
t
CYCLE
Figure14-1
Notes 1.
Or equivalent PREC or PREX command. See Figure 12-2.
2.
This is a constraint imposed by the core, and is therefore in units of ms rather than t
CYCLE
.
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