參數(shù)資料
型號： UPD488448FB-C80-45-DQ1
廠商： NEC Corp.
英文描述： 128 M-bit Direct Rambus⑩ DRAM
中文描述： 128 M位DRAM的直接Rambus的⑩
文件頁數(shù)： 41/80頁
文件大小： 1902K
代理商： UPD488448FB-C80-45-DQ1
Data Sheet M14837EJ3V0DS00
41
μ
PD488448 for Rev. P
Figure 22-1 Control Registers (1/7)
Control Register : INIT
Address : 021
16
15
14
SDE
VID5
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
DIS
TSQ
TEN
LSR
PSR
NSR
SRP
PSX
0
SDEVID4..0
Read/write register.
Reset values are undefined except as affected by SIO Reset as noted below. SETR/CLRR Reset does not affect this register.
Field
Description
Reset
value
SDEVID5..0 Serial Device Identification. Compared to SDEVID5..0 serial address field of serial request packet for register
read/write transactions. This determines which RDRAM is selected for the register read or write operation.
RDRAM disable. DIS=1 causes RDRAM to ignore NAP/PDN exit sequence, DIS=0 permit normal operation.
This mechanism disables an RDRAM.
Temperature Sensing Output. TSQ=1 when a temperature trip point has been exceeded, TSQ=0 when it has
not. TSQ is available during a current control operation (see Figure 25-1).
Temperature Sensing Enable. TEN=1 enables temperature sensing circuitry, permitting the TSQ bit to be
read to determine if a thermal trip point has been exceeded.
Low Power Self-Refresh. LSR=1 enables longer self-refresh interval. The self-refresh supply current is
reduced.
3f
16
DIS
0
TSQ
TEN
0
LSR
0
PSR
PDN Self-Refresh. PSR=1 enables self-refresh in PDN mode. PSR can’t be set while in PDN mode.
0
NSR
NAP Self-Refresh. NSR=1 enables self-refresh in NAP mode. NSR can’t be set while in NAP mode.
0
SRP
SIO Repeater. Controls value on SIO1; SIO1=SIO0 if SRP=1, SIO1=1 if SRP=0.
1
PSX
Power Exit Select. PDN and NAP are exited with (=0) or without (=1) a device address on the DQA5..0 pins.
PDEV5 (on DQA5) selectes broadcast (1) or directed (0) exit. For a dircted exit, PDEV4..0 (on DQA4..0) is
compared to DEVID4..0 to select a device.
Control Register : CNFGA
Address : 023
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PVER5..0=000001
MVER5..0=mmmmmm
DBL1
REFBIT2..0=100
Read only register.
Field
Description
Protocol Version. Specifies the Direct Protocol version used by this device:
0 – Compliant with version 0.62.
1 – Compliant with version 0.7 through this version
2 to 63 – Reserved
PVER5..0
MVER5..0
Manufacturer Version. Specifies the manufacturer identification number.
DBL
Doubled-Bank. DBL=1 means the device uses a doubled-bank architecture with adjacent-bank dependency. DBL=0
means no dependency.
Refresh Bank Bits. Specifies the number of bank address bits to used by REFA and REFP commands.
Permits multi-bank refresh in future RDRAMs.
REFBIT2..0
Caution In RDRAMs with protocol version 1 PVER[5:0] =000001, the range of the PDNX field (PDNX[2:0] in the PDNX
register) may not be large enough to specify the location of the restricted interval in Figure 23-3. In this case,
the effective t
S4
parameter must increase and no row or column packets may overlap the restricted interval.
See Figure 23-3 and Timing conditions table.
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