參數(shù)資料
型號(hào)： UPD488448FB-C80-45-DQ1
廠商： NEC Corp.
英文描述： 128 M-bit Direct Rambus⑩ DRAM
中文描述： 128 M位DRAM的直接Rambus的⑩
文件頁(yè)數(shù)： 34/80頁(yè)
文件大?。?/td> 1902K
代理商： UPD488448FB-C80-45-DQ1
Data Sheet M14837EJ3V0DS00
34
μ
PD488448 for Rev. P
20. Control Register Packets
Table 20-1 summarizes the formats of the four packet
types for control register transactions. Table 20-2
summarizes the fields that are used within the packets.
Figure 20-1 shows the transaction format for the SETR,
CLRR, and SETF commands. These transactions consist
of a single SRQ packet, rather than four packets like the
SWR and SRD commands. The same framing sequence
on the CMD input is used, however. These commands are
used during initialization prior to any control register read
or write transactions.
Table 20-1 Control Register Packet Formats
SCK
Cycle
SIO0 or
SIO1
for SRQ
SIO0 or
SIO1
for SA
SIO0 or
SIO1
for SINT
SIO0 or
SIO1
for SD
SCK
Cycle
SIO0 or
SIO1
for SRQ
SIO0 or
SIO1
for SA
SIO0 or
SIO1
for SINT
SIO0 or
SIO1
for SD
0
1
2
3
4
5
6
7
rsrv
rsrv
rsrv
rsrv
rsrv
SDEV5
SOP3
SOP2
rsrv
rsrv
rsrv
rsrv
SA11
SA10
SA9
SA8
0
0
0
0
0
0
0
0
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
8
9
10
11
12
13
14
15
SOP1
SOP0
SBC
SDEV4
SDEV3
SDEV2
SDEV1
SDEV0
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
0
0
0
0
0
0
0
0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Table 20-2 Field Description for Control Register Packets
Field
Description
rsrv
SOP3..SOP0
Reserved. Should be driven as “0” by controller.
0000 - SRD. Serial read of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.
0001 - SWR. Serial write of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.
0010 - SETR. Set Reset bit, all control registers assume their reset values.
command.
0100 - SETF. Set fast (normal) clock mode. 4 t
SCYCLE
delay until next command.
1011 - CLRR. Clear Reset bit, all control registers retain their reset values.
command.
1111 - NOP. No serial operation.
Note
16 t
SCYCLE
delay until CLRR
Note
4 t
SCYCLE
delay until next
0011, 0101 – 1010, 1100 – 1110 – RSRV. Reserved encodings.
Serial device. Compared to SDEVID5..SDEVID0 field of INIT control register field to select the RDRAM to
which the transaction is directed.
Serial broadcast. When set, RDRAMs ignore {SDEV5..SDEV0} for RDRAM selection.
Serial address. Selects which control register of the selected RDRAM is read or written.
Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM.
SDEV5..SDEV0
SBC
SA11..SA0
SD15..SD0
Note
The SETR and CLRR commands must always be applied in two successive transactions to RDRAMs; i.e. they may not be
used in isolation. This is called “SETR/CLRR Reset”.
Figure 20-1 SETR, CLRR, SETF Transaction
SCK
CMD
SIO0
T
20
SRQ packet - SETR/CLRR/SETF
1111
00000000...00000000
SRQ packet - SETR/CLRR/SETF
0000
SIO1
T
4
The packet is repeated
from SIO0 to SIO1
1
1
1
1
0
0
0
0
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