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參數(shù)資料
| 型號： | UPD488448FB-C80-45-DQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁數(shù)： | 60/80頁 |
| 文件大?。?/td> | 1902K |
| 代理商： | UPD488448FB-C80-45-DQ1 |
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Data Sheet M14837EJ3V0DS00
60
μ
PD488448 for Rev. P
30. RSL Clocking
Figure 30-1 is a timing diagram which shows the detailed requirements for the RSL clock signals on the Channel.
The CTM and CTMN are differential clock inputs used for transmitting information on the DQA and DQB, outputs.
Most timing is measured relative to the points where they cross. The t
CYCLE
parameter is measured from the falling
CTM edge to the falling CTM edge. The t
CL
and t
CH
parameters are measured from falling to rising and rising to falling
edges of CTM. The t
CR
and t
CF
rise-and fall-time parameters are measured at the 20 % and 80 % points.
The CFM and CFMN are differential clock outputs used for receiving information on the DQA, DQB, ROW and COL
outputs. Most timing is measured relative to the points where they cross. The t
CYCLE
parameter is measured from the
falling CFM edge to the falling CFM edge. The t
CL
and t
CH
parameters are measured from falling to rising and rising to
falling edges of CFM. The t
CR
and t
CF
rise- and fall-time parameters are measured at the 20 % and 80 % points. The
t
TR
parameters specifies the phase difference that may be tolerated with respect to the CTM and CFM differential
clock inputs (the CTM pair is always earlier).
Figure 30-1 RSL Timing - Clock Signals
V
CIH
80%
50%
20%
V
CIL
CTM
CTMN
t
CL
t
CH
t
CYCLE
t
CR
t
CF
t
CR
t
CF
V
CIH
80%
50%
20%
V
CIL
CFM
CFMN
t
CR
t
CF
t
CR
t
CF
t
CL
t
CH
t
CYCLE
t
TR
V
X-
V
X-
V
X+
V
X+
V
CM
V
CM
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