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參數(shù)資料
| 型號： | UPD488448FB-C80-45-DQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁數(shù)： | 38/80頁 |
| 文件大?。?/td> | 1902K |
| 代理商： | UPD488448FB-C80-45-DQ1 |
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Data Sheet M14837EJ3V0DS00
38
μ
PD488448 for Rev. P
7.0 Other RDRAM Register Fields
This stage rewrites the INIT register with the final values of the LSR, NSR, and PSR fields.
In essence, the controller must read all the read-only configuration registers of all RDRAMs (or it must read the
SPD device present on each RIMM), it must process this information, and then it must write all the read-write
registers to place the RDRAMs into the proper operating mode.
Initialization Note :
1. During the initialization process, it is necessary for the controller to perform 128 current control operations
(3xCAL, 1xCAL/SAM) and one temperature calibrate operation (TCEN/TCAL) after reset or after powerdown
(PDN) exit.
2. The behavior of
μ
PD488448 Rev. P at initialization is as follows. It is distinguished by the "S28IECO" bit in the
SPD.
S28IECO=1: Upon powerup, the device enters PDN state. The serial operations SETR, CLRR, and SETF
require a SDEVID match.
See the document detailing the reference initialization procedure for more information on how to handle this in
a system.
3. After the step of equalizing the total read delay of each RDRAM has been completed (i.e. after the TCDLY0
and TCDLY1 fields have been written for the final time), a single final memory read transaction should be
made to each RDRAM in order to ensure that the output pipeline stages have been cleared.
4. The SETF command (in the serial SRQ packet) should only be issued once during the Initialization process,
as should the SETR and CLRR commands.
5. The CLRR command (in the serial SRQ packet) leaves some of the contents of the memory core in an
indeterminate state.
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