參數(shù)資料
型號： UPD488448FB-C80-45-DQ1
廠商： NEC Corp.
英文描述： 128 M-bit Direct Rambus⑩ DRAM
中文描述： 128 M位DRAM的直接Rambus的⑩
文件頁數(shù)： 57/80頁
文件大?。?/td> 1902K
代理商： UPD488448FB-C80-45-DQ1
Data Sheet M14837EJ3V0DS00
57
μ
PD488448 for Rev. P
27. Timing Conditions
Timing Conditions
Symbol
Parameter
MIN.
MAX.
Unit
Figures
t
CYCLE
CTM and CFM cycle times
-C60
3.33
3.83
ns
Figure 30-1
-C71
2.81
3.83
-C80
2.50
3.83
t
CR
, t
CF
CTM and CFM input rise and fall times
0.2
0.5
ns
Figure 30-1
t
CH
, t
CL
CTM and CFM high and low times
40%
60%
t
CYCLE
Figure 30-1
t
TR
CTM-CFM differential
(MSE/MS=0/0)
0.0
1.0
t
CYCLE
Figure 22-1
(MSE/MS=1/1)
Note1
0.9
1.0
Figure 30-1
t
DCW
Domain crossing window
–0.1
+0.1
t
CYCLE
Figure 35-1
t
DR
, t
DF
DQA/DQB/ROW/COL input rise/fall times
0.2
0.65
ns
Figure 31-1
t
S
, t
H
DQA/DQB/ROW/COL-to-CFM
t
CYCLE
=2.50ns
0.200
Note4
—
ns
Figure 31-1
setup/hold time
t
CYCLE
=2.81ns
0.240
Note3,4
—
t
CYCLE
=3.33ns
0.275
Note2,4
—
t
DR1
, t
DF1
SIO0, SIO1 input rise and fall times
—
5.0
ns
Figure 33-1
t
DR2,
t
DF2
CMD,SCK input rise and fall times
—
2.0
ns
Figure 33-1
t
CYCLE1
SCK cycle time - Serial control register transactions
1,000
—
ns
Figure 33-1
SCK cycle time - Power transitions
10
—
ns
Figure 33-1
t
CH1
, t
CL1
SCK high and low times
4.25
—
ns
Figure 33-1
t
S1
CMD setup time to SCK rising or falling edge
Note5
1.25
—
ns
Figure 33-1
t
H1
CMD hold time to SCK rising or falling edge
Note5
1
—
ns
Figure 33-1
t
S2
SIO0
setup time to SCK falling edge
40
—
ns
Figure 33-1
t
H2
SIO0
hold time to SCK falling edge
40
—
ns
Figure 33-1
t
S3
PDEV setup time on DQA5..0 to SCK rising edge
0
—
ns
Figure 23-4, 33-2
t
H3
PDEV hold time on DQA5..0 to SCK rising edge
5.5
—
ns
Figure 23-4, 33-2
t
S4
ROW2..0, COL4..0 setup time for quiet window
Note6
–1
—
t
CYCLE
Figure 23-4
t
H4
ROW2..0, COL4..0 hold time for quiet window
5
—
t
CYCLE
Figure 23-4
V
IL, CMOS
CMOS input low voltage - over / undershoot voltage
duration is less than or equal to 5 ns
CMOS input high voltage - over / undershoot voltage
duration is less than or equal to 5ns
Quiet on ROW / COL bits during NAP / PDN entry
–0.7
+(V
CMOS
/2–0.6)
V
V
IH, CMOS
V
CMOS
/2 + 0.6
V
CMOS
+ 0.7
V
t
NPQ
4
—
t
CYCLE
Figure 23-3
t
READTOCC
Offset between read data and CC packets (same device)
12
—
t
CYCLE
Figure 25-1
t
CCSAMTOREAD
Offset between CC packet and read data (same device)
8
—
t
CYCLE
Figure 25-1
t
CE
CTM/CFM stable before NAP/PDN exit
2
—
t
CYCLE
Figure 23-4
t
CD
CTM/CFM stable after NAP/PDN entry
100
—
t
CYCLE
Figure 23-3
t
FRM
ROW packet to COL packet ATTN framing delay
7
—
t
CYCLE
Figure 23-2
t
NLIMIT
Maximum time in NAP mode
—
10
μs
ms
Figure 23-1
t
REF
Refresh interval
—
32
Figure 24-1
t
CCTRL
Current control interval
34 t
CYCLE
100 ms
—
Figure 25-1
t
TEMP
Temperature control interval
—
100
ms
Figure 25-2
t
TCEN
TCE command to TCAL command
150
—
t
CYCLE
Figure 25-2
t
TCAL
TCAL command to quiet window
2
2
t
CYCLE
Figure 25-2
t
TCQUIET
Quiet window (no read data)
140
—
t
CYCLE
Figure 25-2
t
PAUSE
t
BURST
RDRAM delay (no RSL operations allowed)
Interval after PDN or NAP (with self-refresh) exit in which
all banks of the RDRAM must be refreshed at least once.
—
—
200
200
μs
μs
Figure 22-1
Figure 24-2
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