- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379500 > UPD488448FB-C80-45-DQ1 (NEC Corp.) 128 M-bit Direct Rambus⑩ DRAM PDF資料下載
參數(shù)資料
| 型號： | UPD488448FB-C80-45-DQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁數(shù)： | 55/80頁 |
| 文件大?。?/td> | 1902K |
| 代理商： | UPD488448FB-C80-45-DQ1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
Data Sheet M14837EJ3V0DS00
55
μ
PD488448 for Rev. P
25. Current and Temperature Control
Figure 25-1 shows an example of a transaction which performs current control calibration. It is necessary to
perform this operation once to every RDRAM in every t
CCTRL
interval in order to keep the I
OL
output current in its
proper range.
This example uses four COLX packets with a CAL command. These cause the RDRAM to drive four calibration
packets Q(a0) a time t
CAC
later. An offset of t
RDTOCC
must be placed between the Q(a0) packet and read data Q(a1)
from the same device. These calibration packets are driven on the DQA4..3 and DQB4..3 wires. The TSQ bit of the
INIT register is driven on the DQA5 wire during same interval as the calibration packets. The remaining DQA and
DQB wires are not used during these calibration packets. The last COLX packet also contains a SAM command
(concatenated with the CAL command). The RDRAM samples the last calibration packet and adjusts its I
OL
current
value.
Unlike REF commands, CAL and SAM commands cannot be broadcast. This is because the calibration packets
from different devices would interfere. Therefore, a current control transaction must be sent every t
CCTRL
/N, where N
is the number of RDRAMs on the Channel. The device field Da of the address a0 in the CAL/SAM command should
be incremented after each transaction.
Figure 25-2 shows an example of a temperature calibration sequence to the RDRAM. This sequence is broadcast
once every t
TEMP
interval to all the RDRAMs on the Channel. The TCEN and TCAL are ROP commands, and cause
the slew rate of the output drivers to adjust for temperature drift. During the quiet interval t
TCQUIET
the devices being
calibrated can’t be read, but they can be written.
Figure 25-1 Current Control CAL/SAM Transaction Example
CTM/CFM
DQA7..0
DQB7..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
Transaction a0: CAL/SAM
Transaction a1: RD
Transaction a2: CAL/SAM
a0 = {Da, Bx}
a1 = {Da, Bx}
a2 = {Da, Bx}
t
CCTRL
CAL a0
CAL a2
Q (a0)
t
CAC
CAL a0
CAL a0
CAL/SAM a0
Read data from a different
device from an earlier RD
command can be anywhere
prior to the Q(a0) packet.
Read data from a different
device from a later RD
command can be anywhere
after to the Q(a0) packet.
Read data from the same
device from a later RD
command must be at this
packet position or later.
Read data from the same
device from an earlier RD
command must be at this
packet position or earier.
DQA5 of the first calibrate packet has the inverted TSQ bit of INIT
control register; i.e. logic 0 or high voltage means hot temperature.
When used for monitoring, it should be enabled with the DQA3
bit (current control one value) in case there is no RDRAM present:
HotTemp = /DQA5
DQA3
Note
that DQB3 could be used instead of DQA3.
t
READTOCC
Q (a1)
Q (a1)
CCSAMTOREAD
t
Figure 25-2 Temperature Calibration (TCEN-TCAL) Transactions to RDRAM
CTM/CFM
DQA7..0
DQB7..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
CAL
TCEN
TCAL
TCEN
t
TCAL
Any ROW packet may be
placed in the gap between the
ROW packets with the
TCEN and TCAL commands.
No read data from devices
being calibrated
t
TEMP
t
TCEN
t
TCQUIET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD488448FB-C80-45-DQ2 | 128 M-bit Direct Rambus⑩ DRAM |
| UPD488448FB-C71-45-DQ1 | 128 M-bit Direct Rambus⑩ DRAM |
| UPD488448FB-C71-45-DQ2 | 128 M-bit Direct Rambus⑩ DRAM |
| UPD488448FB-C60-53-DQ2 | 128 M-bit Direct Rambus⑩ DRAM |
| UPD488448FF-C80-45-DQ1 | 128 M-bit Direct Rambus⑩ DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD4990AG-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD4991ACX-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD4992CX-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD50256CP15 | 制造商:HIT 功能描述:50256 HITACHI'86 SMT N9F8A |
| UPD50256CP-15 | 制造商:HIT 功能描述:50256 HITACHI'86 SMT N9F8A |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。