
DS3112
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6.3 T2 / E2 / G747 FRAMER STATUS AND INTERRUPT REGISTER
DESCRIPTION
Register Name:
T2E2SR1
Register Description:
T2/E2 Status Register 1
Register Address:
34h
Bit #
7
654
321
0
Name
IELOF
LOF7
LOF6
LOF5
LOF4
LOF3
LOF2
LOF1
Default
0
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Bit #
15
141312
1110
9
8
Name
IEAIS
AIS7
AIS6
AIS5
AIS4
AIS3
AIS2
AIS1
Default
0
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-
Note: See Figure 6.3A for details on the signal flow for the status bits in the T2E2SR1 register.
Note: Bits that are underlined are read only; all other bits are read-write.
Bits 0 to 6 / Loss Of Frame Occurrence (LOFn when n = 1 to 7). This latched read only alarm status
bit will be set to a one each time the corresponding T2/E2/G747 framer detects a Loss Of Frame (LOF).
This bit will be cleared when read unless a LOF condition still exists in that T2/E2/G747 framer. A
change in state of the LOF in one or more of the T2/E2/G747 framers can cause the T2E2SR1 status bit
(in the MSR register) to be set and a hardware interrupt to occur if the IELOF bit is set to a one and the
T2E2SR1 bit in the Interrupt Mask for MSR (IMSR) register is set to a one.
See Figure 6.3A. The
interrupt will be allowed to clear when this bit is read. The LOF alarm criteria is described in Tables
6.3A, 6.3B and 6.3C. In the E3 Mode, LOF5 to LOF7 (bits 4 to 6) are meaningless and should be
ignored.
Bit 7 / Interrupt Enable for Loss of Frame Occurrence (IELOF). This bit should be set to one if the
Host wishes to have T2/E2/G747 LOF occurrences cause a hardware interrupt or the setting of the
T2E2SR1 status bit in the MSR register. See Figure 6.3A. The T2E2SR1 bit in the Interrupt Mask for the
Master Status Register (IMSR) must also be set to one for an interrupt to occur.
0 = interrupt masked
1 = interrupt unmasked
Bits 8 to 14 / Alarm Indication Signal Detected (AISn when n = 1 to 7). This latched read only alarm
status bit will be set to a one each time the corresponding T2/E2/G747 framer detects an incoming AIS
alarm. This bit will be cleared when read unless the AIS alarm still exists in that T2/E2/G747 framer. A
change in state of the AIS detector in one or more of the T2/E2/G747 framers can cause the T2E2SR1
status bit (in the MSR register) to be set and a hardware interrupt to occur if the IEAIS bit is set to a one
and the T2E2SR1 bit in the Interrupt Mask for MSR (IMSR) register is set to a one. See Figure 6.3A.
The interrupt will be allowed to clear when this bit is read. The AIS alarm criteria is described in Tables
6.3A, 6.3B and 6.3C. In the E3 Mode, AIS5 to AIS7 (bits 4 to 6) are meaningless and should be ignored.
Bit 15 / Interrupt Enable for Alarm Indication Signal (IEAIS). This bit should be set to one if the
Host wishes to have T2/E2/G747 AIS detection occurrences cause a hardware interrupt or the setting of
the T2E2SR1 status bit in the MSR register. See Figure 6.3A. The T2E2SR1 bit in the Interrupt Mask for
the Master Status Register (IMSR) must also be set to one for an interrupt to occur.
0 = interrupt masked
1 = interrupt unmasked