參數(shù)資料
型號(hào)： DS3112N
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 4/134頁
文件大小： 900K
代理商： DS3112N
DS3112
101 of 134
Bits 0 to 5 / Transmit FEAC Codeword A Data (TFCA0 to TFCA5). The FEAC codeword is of the
form ...0xxxxxx011111111... where the rightmost bit is transmitted first. These six bits are the middle six
bits of the second byte of the FEAC codeword (i.e. the six “x” bits). The device can generate two
different codewords and these six bits represent what will be transmitted for codeword A. TFCA0 is the
LSB and is transmitted first while TFCA5 is the MSB and is transmitted last. The TFS0 and TFS1
control bits determine if this codeword is to be generated. These bits should only be changed when the
transmit FEAC controller is in the idle state (TFS0 = 0 and TFS1 = 0).
Bits 6 and 7 / Transmit FEAC Codeword Select Bits 0 and 1 (TFS0 and TFS1). These two bits
control which of the two available codewords are to be generated. Both TFS0 and TFS1 are edge
triggered. To change the action, the Host must go back to the null state (TFS0 = TFS1 = 0) before
proceeding to the desired action.
TFS1
TFS0
Action
0
idle state; do not generate a FEAC codeword (send all ones)
0
1
send 10 of codeword A followed by all ones
1
0
send 10 of codeword A followed by 10 of codeword B followed by all ones
1
send codeword A continuously (will be sent for at least 10 times)
Bits 8 to 13 / Transmit FEAC Codeword B Data (TFCB0 to TFCB5). The FEAC codeword is of the
form ...0xxxxxx011111111... where the rightmost bit is transmitted first. These six bits are the middle six
bits of the second byte of the FEAC codeword (i.e. the six “x” bits). The device can generate two
different codewords and these six bits represent what will be transmitted for codeword B. TFCB0 is the
LSB and is transmitted first while TFCB5 is the MSB and is transmitted last. The TFS0 and TFS1
control bits determine if this codeword is to be generated. These bits should only be changed when the
transmit FEAC controller is in the idle state (TFS0 = 0 and TFS1 = 0).
Bit 14 / Interrupt Enable, Receive FEAC Idle (IERFI). This bit masks or enables interrupts caused by
the Receive FEAC Idle (RFI) bit in the FSR register.
0 = interrupt masked
1 = interrupt unmasked
Bit 15 / Receive FEAC Controller Reset (RFR). A 0 to 1 transition will reset the receive FEAC
controller and flush the Receive FEAC FIFO. This bit must be cleared and set again for a subsequent
reset.
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參數(shù)描述
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DS3112ND1E 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
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