參數(shù)資料
型號: DS3112N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 93/134頁
文件大?。?/td> 900K
代理商: DS3112N
DS3112
61 of 134
Register Name:
EXZCR
Register Description:
EXcessive Zero Count Register
Register Address:
22h
Bit #
765
43210
Name
EXZ7
EXZ6
EXZ5
EXZ4
EXZ3
EXZ2
EXZ1
EXZ0
Default
---
-----
Bit #
151413
121110
9
8
Name
EXZ15
EXZ14
EXZ13
EXZ12
EXZ11
EXZ10
EXZ9
EXZ8
Default
---
-----
Note: Bits that are underlined are read only; all other bits are read-write.
Bits 0 to 15 / 16-Bit EXcessive Zero Counter (EXZ0 to EXZ15). These bits report the number of
EXcessive Zero occurrences (EXZ). An EXZ occurrence is defined as three or more consecutive zeros in
the T3 Mode and four or more consecutive zeros in the E3 Mode. As an example, a string of eight
consecutive zeros would only increment this counter once.
Register Name:
FECR
Register Description:
Frame Error Count Register
Register Address:
24h
Bit #
765
43210
Name
FE7
FE6
FE5
FE4
FE3
FE2
FE1
FE0
Default
---
-----
Bit #
151413
121110
9
8
Name
FE15
FE14
FE13
FE12
FE11
FE10
FE9
FE8
Default
---
-----
Note: Bits that are underlined are read only; all other bits are read-write.
Bits 0 to 15 / 16-Bit Framing Bit Error Counter (FE0 to FE15). These bits report either the number of
Loss Of Frame (LOF) occurrences or the number of framing bit errors received. The FECR is configured
via the Host by the Frame Error Counting Control Bits (FECC0 and FECC1) in the T3E3 Control
Register (see Section 5.2). The possible configurations are shown below.
FECC1
FECC0
Frame Error Count Register (FECR) Configuration
00
T3 Mode: count Loss Of Frame (LOF) Occurrences
E3 Mode: count Loss Of Frame (LOF) Occurrences
01
T3 Mode: count both F bit and M bit errors
E3 Mode: count bit errors in the FAS word
10
T3 Mode: count only F bit errors
E3 Mode: count word errors in the FAS word
11
T3 Mode: count only M bit errors
E3 Mode: illegal state
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