參數(shù)資料
型號: DS3112N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 24/134頁
文件大小: 900K
代理商: DS3112N
DS3112
12 of 134
Lead
Symbol
Type
Signal Description
F1
CD12
I/O
CPU Bus Data Bit 12.
G3
CD13
I/O
CPU Bus Data Bit 13.
G2
CD14
I/O
CPU Bus Data Bit 14.
G1
CD15
I/O
CPU Bus Data Bit 15. MSB.
B3
CIM
I
CPU Bus Intel/Motorola Bus Select. 0 = INTEL,
1 = MOT.
A2
CINT*
O
CPU Bus Interrupt.
B2
CMS
I
CPU Bus Mode Select. 0 = 16 Bit, 1 = 8 Bit Mode.
D5
CRD*(CDS*)
I
CPU Bus Read Enable (CPU Bus Data Strobe).
A3
CWR*(CR/W*)
I
CPU Bus Write Enable (CPU Bus Read/Write Select).
A9
FRCLK
O
Receive Framer (T3 or E3) Clock Output.
B9
FRD
O
Receive Framer (T3 or E3) Data Output.
C9
FRDEN
O
Receive Framer (T3 or E3) Data Enable Output.
C8
FRLOF
O
Receive Framer (T3 or E3) Loss Of Frame Output.
B8
FRLOS
O
Receive Framer (T3 or E3) Loss Of Signal Output.
A7
FRMECU
I
Receive Framer (T3 or E3) Manual Error Counter Update.
A8
FRSOF
O
Receive Framer (T3 or E3) Start Of Frame Pulse.
A10
FTCLK
I
Transmit Framer (T3 or E3) Clock Input.
B10
FTD
I
Transmit Framer (T3 or E3) Data Input.
C10
FTDEN
O
Transmit Framer (T3 or E3) Data Enable Output.
C11
FTMEI
I
Transmit Framer (T3 or E3) Manual Error Insert Pulse.
A11
FTSOF
I/O
Transmit Framer (T3 or E3) Start Of Frame Pulse.
B6
G747E
I
G747 Mode Enable. 0 = Normal T3 Mode, 1 = G747
Mode.
A13
HRCLK
I
High Speed (T3 or E3) Port Receive Clock Input.
C12
HRNEG
I
High Speed (T3 or E3) Port Receive Negative Data Input.
B13
HRPOS
I
High Speed (T3 or E3) Port Receive Positive or NRZ Data
Input.
B14
HTCLK
O
High Speed (T3 or E3) Port Transmit Clock Output.
A14
HTNEG
O
High Speed (T3 or E3) Port Transmit Negative Data
Output.
C14
HTPOS
O
High Speed (T3 or E3) Port Transmit Positive or NRZ
Data Output.
D7
JTCLK
I
JTAG IEEE 1149.1 Test Serial Clock.
B5
JTDI
I
JTAG IEEE 1149.1 Test Serial Data Input.
A4
JTDO
O
JTAG IEEE 1149.1 Test Serial Data Output.
A5
JTMS
I
JTAG IEEE 1149.1 Test Mode Select.
C6
JTRST*
I
JTAG IEEE 1149.1 Test Reset.
G20
LRCCLK
I
Low Speed (T1 or E1) Port Common Receive Clock Input.
N2
LRCLK1
O
Low Speed (T1 or E1) Receive Clock from Port 1.
R1
LRCLK2
O
Low Speed (T1 or E1) Receive Clock from Port 2.
R3
LRCLK3
O
Low Speed (T1 or E1) Receive Clock from Port 3.
U2
LRCLK4
O
Low Speed (T1 or E1) Receive Clock from Port 4.
V2
LRCLK5
O
Low Speed (T1 or E1) Receive Clock from Port 5.
Y2
LRCLK6
O
Low Speed (T1 or E1) Receive Clock from Port 6.
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