參數(shù)資料
型號: DS3112N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 81/134頁
文件大?。?/td> 900K
代理商: DS3112N
DS3112
50 of 134
Bit 11 / Error Counting Control (ECC). This bit is used to control whether the device will increment
the error counters during Loss Of Frame (LOF) conditions. It only affects the error counters that count
errors that are based on framed information and these include the following:
Frame Error Counter (when it is configured to count frame errors, not LOF occurrences)
T3 Parity Bit Error Counter
T3 C-Bit Parity Error Counter
T3 Far End Block Error or E3 RAI Counter.
When this bit is set low, these error counters will not be allowed to increment during LOF conditions.
When this bit is set high, these error counters will be allowed to increment during LOF conditions.
0 = stop the FECR/PCR/CPCR/FEBECR error counters from incrementing during LOF
1 = allow the FECR/PCR/CPCR/FEBECR error counters to increment during LOF
Bit 12 / Automatic FEBE Defeat (AFEBED). This bit is ignored in the E3 Mode and in the T3 Mode
when the device is not configured in the C-Bit Parity Mode. When this bit is low, the device will
automatically insert the FEBE codes into the transmitted data stream by setting all three C Bits in
Subframe 4 to zero.
0 = automatically insert FEBE codes in the transmit data stream based on detected errors
1 = use the TFEBE control to determine the state of the FEBE codes
Bit 13 / Transmit FEBE Setting (TFEBE). This bit is only active when AFEBED is active (i.e.
AFEBED = 1). When this bit is low, the device will force the FEBE code to 111 continuously. When
this bit is set high, the device will force the FEBE code to 000 continuously.
0 = force FEBE to 111 (null state)
1 = force FEBE to 000 (active state)
Bit 14 / T3/E3 Payload Loopback Enable (PLB). See Figures 1A and 1B for a visual description of
this loopback.
0 = disable loopback
1 = enable loopback
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參數(shù)描述
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