參數(shù)資料
型號: DS3112N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 7/134頁
文件大小: 900K
代理商: DS3112N
DS3112
104 of 134
11.2 TAP CONTROLLER STATE MACHINE DESCRIPTION
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine.
Please See Figure 11.2A for details on each of the states described below. The TAP controller is a finite
state machine which responds to the logic level at JTMS on the rising edge of JTCLK.
TAP Controller State Machine Figure 11.2A
Test-Logic-Reset
Upon power-up of the DS3112, the TAP controller will be in the Test-Logic-Reset state. The Instruction
register will contain the IDCODE instruction. All system logic on the DS3112 will operate normally.
Run-Test-Idle
Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and Test
register will remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the
controller into the Capture-DR state and will initiate a scan sequence. JTMS high moves the controller to
the Select-IR-SCAN state.
Test-Logic-Reset
Run-Test/Idle
Select
DR-Scan
1
0
Capture-DR
1
0
Shift-DR
0
1
Exit1- DR
1
0
Pause-DR
1
Exit2-DR
1
Update-DR
0
1
Select
IR-Scan
1
0
Capture-IR
0
Shift-IR
0
1
Exit1-IR
1
0
Pause-IR
1
Exit2-IR
1
Update-IR
0
1
0
1
0
1
0
1
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